Gate-level simulation reported timing violations which were not reported in STA

[Altera_Forum]

Hi, 

 As the title says, modelsim reported a lot of timing violations during the gate-level simulation. However the same design passed STA. I used the same clk frequency in the simulation as in the timing constraint, I also tried slower frequency in the simulation and that generated even more timing violations. How did that happen? How should I deal with it?  Thanks!

[Altera_Forum]

Timing violations can be e.g. caused by unconstrained external signals or asynchronous logic that isn't covered by timing constraints. You should analyze the nature of the timing violations.

[Altera_Forum]

Thanks for the reply. 

Turns out the violations were due to unconstrained i/o paths. The violations disappeared when I added constraints with random parameters. Could you advice me how to determine input/output delay for specified demo board? I'm currently implementing a NIOS system on a Terasic de4 board. Is there any document I can take reference from?