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Generate PCI Express Example Design Errors

Jerry4
Beginner
166 Views

Hi, I want to  generate intel L-/H- Tile Avalon memory mapped for PCIe IP example,
but there are some errors:
Error: pcie_s10_hip_avmm_bridge_0: Failed pcie_ed.qsys simulation generation
Error: pcie_s10_hip_avmm_bridge_0: Unable to generate HDL files for the system pcie_ed.qsys
Error: add_fileset_file: No such file C:/Users/admin/AppData/Local/Temp/alt8997_8184405479883526907.dir/0002_pcie_s10_hip_avmm_bridge_0_gen/ip/pcie_ed/pcie_ed_jtag_to_master_avalon_bridge/altera_jtag_avalon_master_191/sim/pcie_ed_jtag_to_master_avalon_bridge_altera_jtag_avalon_master_191_3zppvky.v/pcie_ed_jtag_to_master_avalon_bridge_altera_jtag_avalon_master_191_3zppvky.v
while executing
"add_fileset_file $relative_item [ ::altera_pcie_s10_hip_avmm_bridge::fileset::filetype $absolute_path ] PATH $absolute_path"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $relative_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line 6)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $relative_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line 6)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $relative_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line 6)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $relative_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line 6)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $relative_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker" line 6)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::folder_worker $top_item"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::add_files_recurs..." line 7)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::add_files_recursive [ pwd ]"
(procedure "::altera_pcie_s10_hip_avmm_bridge::generate_design_example_f..." line 63)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::generate_design_example_files ${QSYSTemPath} ${QSYSTemName}"
(procedure "::altera_pcie_s10_hip_avmm_bridge::generate_dynamic_qsys" line 671)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::generate_dynamic_qsys"
(procedure "::altera_pcie_s10_hip_avmm_bridge::dynamic_example_design" line 97)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::dynamic_example_design"
(procedure "::altera_pcie_s10_hip_avmm_bridge::fileset::callback_example..." line 2)
invoked from within
"::altera_pcie_s10_hip_avmm_bridge::fileset::callback_example_design pcie_s10_hip_avmm_bridge_0_example_design"
Error: Failed to generate example design example_design to: F:\quartus\demopci\Device\pcie_s10_hip_avmm_bridge_0_example_design


The configuration is as follows:
Desgin Environment:System
Hard IP Mode:Gen3x8
Port type:Root Port
Enable Avalon-MM DMA
Instantiate internal descriptor controller:disable
Enable control register access (CRA) Avalon-MM slave port
Export MSI/MSI-X conduit interfaces
Enable Avalon-MM Slave interface with individual byte access. (TXS).
Address width of accessible PCIe memory space(TXS):32
Enable High Performance bursting Avalon-MM Slave interface (HPTXS).
Enable mapping (HPTXS):disable
Address width of accessible PCIe memory space (HPTXS):32
Enable HIP dynamic reconfiguration of PCIe read-only registers
Enable Transceiver dynamic reconfiguration
Enable Native PHY, ATXPLL and fPLL ADME for Transceiver Toolkit
Enable PCIe Link Inspector
Enable PCIe Link Inspector AVMM Interface

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