Hi..I am using Quartus II. I am able to complete analysis and synthesis. Now I wanted to get post synthesis netlist so that I can run simulation on this post synthesis netlist and verify whether synthesis has generated correct netlist or not. I am not been able to find how to access post synthesis netlist after synthesis step. Kindly tell me how can I do this with Quartus II. Thanks for help!!!! Prashant
Hi prashant,The solution below answers your question: http://www.altera.com/support/kdb/solutions/rd10192005_405.html For more information on what values are available for -format and -tool option, you can type quartus_eda --help=format quartus_eda --help=tool on the command line.
Hi Golgo,Thanks for your reply. I am currently using 2-port ROM and intializing it using *.hex file. I am able to simulate pre-synthesis file using Modelsim. I then synthesized the code and then try running it using Modelsim. I found that post synthesis ROM is not been initialized. Please let me know how to correct this. Thanks for your time Prashant
Are you sure the synthesis is reading in the .hex files? Look at the Fitter Report -> Resource Section -> Ram Summary under the MIF(Memory Initialization File, but it will also show .hex files) for that particular ROM. If it says None, it was never read in. I believe(but am not positive) that once it gets read in, the initialization should be in the post-synthesis netlist and you shouldn't have to re-read any initialization files.
Hi Rysc,Thanks for the reply. I have seen checked the "Fitter Report -> Resource Section -> Ram Summary" It shows the .hex file path, but still I am not able get ROM working in post synthesis simulation. Please help me..
You say a post-synthesis simulation? Do you mean post-fit? Are you writing a .vho/vo and .sdo file out? I looked at a design I have with initialization files, and created a .vo file for modelsim. When I search through this, I see the memories called out(at the block level, e.g. if it takes 8 M4Ks in the fit, then there will be 8 separate M4Ks called out) but they all have an .mem_init parameter with initialization values in them. So I assume all the info is there, although I'm not actually simulating the design. Please make sure you have an SR opened on this, so someone can help you debug it.
Hi Rysc.Thanks for your reply. I am using *.vo fileout for the simulation. I am able to see data in the mem_init line but when I simulate it in Modelsim the output of this memory block is always 000000. Please let me know how should I proceed to answer this ? I am not been able to understand the meaning of the quote below. --- Quote Start --- I am doing post-synthesis simulation so that I have better confidence that the code that I have written is synthesized properly.
I'm not sure why you're not seeing the initialization occur. It's almost as if modelsim isn't reading in that mem_init line.An SR is a service request, i.e. it goes to an apps engineer who will work with you on resolving the problem(as opposed to a forum, which is based on the kindness of strangers, i.e. help will only go so far). You may want to create a simple test case, such as a design with a single initialized RAM, the produced .vo file, the testbench that reads from a location, and the .do file to run Modelsim and show that 0s are coming out. That way the apps engineer should be able to quickly recreate what you're seeing. (You might be able to put the example up here, too, but again you're relying on someone to voluntarily try it out.) Good luck.