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15555 Discussions

Generate a bianry code from an integer array?

Honored Contributor II



I am trying to work for first time with integer arrays. I am not so used to work with them, and I am not able to compile my code.  


At first, I have created a package, for the arrays of integers: 



--- Quote Start ---  

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.numeric_std.all; 


PACKAGE inputnumberrs IS 

constant longitude : integer := 4; 

type num is array (longitude-1 to 0) of integer; 



--- Quote End ---  



BTW, I suppose that I will be able to modify this "longitude" constant for another number in ModelSim, right? Forcing the signal or something i suppose. 


Then, I have created the entity of another project:  



--- Quote Start ---  


entity generator is 

generic (longitude : integer := 4); 

port (X, Y : in num; 

clk : in std_logic); 

end generator; 


--- Quote End ---  



And what I want to do is, for example, itroducing 2314 to X and to generate "0010 0011 0001 0100", so I have tryied this: 



--- Quote Start ---  



architecture Behavioral of generator is 


signal t, u : integer := 0; 

signal a,b : std_logic_vector (longitude*longitude downto 0); 







wait until CLK'EVENT and CLK = '1'; 

for i in 0 to (longitud*longitud) loop 


a(u)<= std_logic_vector(to_unsigned(x,4));  

t<= t+1; 

u <= u + 4 ;  


end loop; 


end process; 

end behavioral; 

--- Quote End ---  



The compilation error I get is : Error (10409): VHDL Type Conversion error at generar_numeros.vhd(40): converted type of object near text or symbol "std_logic_vector" must match std_ulogic type of target object 


and i do not have any idea why it is not compiling. If I write a <= std_logic_vector(to_unsigned(x,4)); , withouth the (U), it compiles but does not work :( Any suggestions?
0 Kudos
2 Replies
Honored Contributor II

Several issues in the code: 

1. Your Num type is a null array (ie, it has 0 length) 

type num is array (longitude-1 to 0) of integer; 


This is a null array, so has length 0. with an ascending array (using to), the larger number must be on the right. So you need to use: 


type num is array (0 to longitude-1) of integer; 


A a descending array (using downto) is the opposite. 


2. You have a longitude generic, but the length of the num type is set in the package. So having longitude generic set to anything other than 4 will not work. PS. having a generic called longitude means you've hidden the longitude constant in the inputnumberrs package  


3. Your a and b slvs are (16 downto 0) ie. 17 bits long. Did you forget the -1? 


4. a(u) is a single bit, the 0th element of the a slv. Also, x is an array of integers. to_unsigned only convers a single integer. You also are using the literal 4, when you should probably be using the generic or constant (see issues above) 

5. why have you got a for loop, when you dont use the loop variable, i? 

6. I assume this is test code, as this will not synthesis as you have a wait statement at the end of the process. So on the first clock, you set a value of A, and then thats it? 

7. t is unused. 



a <= std_logic_vector(to_unsigned(x,4)) cannot be working with the code you posted, as X is an array of 4 integers, and no to_unsigned function exists to convert multiple integers, unless you have defined it yourself. 


So, is this just test code? it cannot work on an FPGA.
Honored Contributor II

You are assigning a bit vector to a single bit which isn't possible, a simple issue of VHDL syntax. 


You want to write something like 

a(u+3 downto u)<= std_logic_vector(to_unsigned(x,4)); 



--- Quote Start ---  

And what I want to do is, for example, introducing 2314 to X and to generate "0010 0011 0001 0100", so I have tryied this: 


--- Quote End ---  


2314 isn't an array of integer literal, it's either a decimal value or a string respectively character array.