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Generating a Simulation File for ATLPLL IP

kh12
New Contributor I
759 Views

Hello, I am using the MAX10 dev board. Following instructions for creating the PLL is easy, however as seen in the following document (https://www.ece.ucdavis.edu/~bbaas/180/tutorials/using.a.PLL.pdf) walking through the creation of the PLL, there are no options to generate simulation files? I used to be able to do this, but now do not know how. Does anyone have any ideas??

 

 

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ShengN_Intel
Employee
712 Views

Hi,

 

Go to Assignments > Settings > EDA Tool Settings > Simulation. Then set Tool name and EDA Netlist Writer settings. Should see simulation file generated after EDA Netlist Writer compilation. Remember to set the Tool Executable location in Tools > Options > EDA Tool Options

 

Best Regards,

Sheng

 

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

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kh12
New Contributor I
703 Views

Hello,

 

I am looking to generate a verilog file to run on modelsim. With past versions (using altera pll instead of ALTPLL) I used to get a folder like: pllname_0002 and in it I had a .qip file and a .v file. When I follow these instructions I don't get that simulation verilog file.

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ShengN_Intel
Employee
685 Views

Hi,

 

ALTPLL does generate .qip and .v files. Both ALTPLL and altera pll got the simulation file generated after the steps and EDA Netlist Writer compilation. The simulation file got the .vo (verilog) and .do files. For ALTPLL simulation setup script, you probably need to generate it through platform designer. Check the folders attached.

Check this document https://www.intel.com/content/www/us/en/docs/programmable/683080/18-1/generating-ip-simulation-files.html probably can help you.

  • Intel® FPGA IP cores that do not require IP functional simulation models for simulation, do not provide the Generate Simulation Model option in the IP core parameter editor.

ALTPLL simulation design examples:

https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/functional-results-simulate-the-ddr.html

https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/simulating-the-shift-clk-design-in-the.html

 

Thanks,

Best Regards,

Sheng

 

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kh12
New Contributor I
653 Views

Hello Sheng,

 

Could you explain what the ALTPLL simulation setup script means? you say .do and .vo simulation files get generated, what is the difference between these and simulation setup scripts?

When I go to ModelSim I am unable to get the simulation to work using the .v file, and putting the .do and .vo files in the simulation project directory also doesnt help.

 

Let me reframe my question maybe. I am running a design that uses a pll to transform 50 MHz into 40MHz. How can I get the PLL to work on modelsim? which files are needed? this is still unclear to me.

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ShengN_Intel
Employee
658 Views

Hi,


Any further update or consideration?


Best Regards,

Sheng


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ShengN_Intel
Employee
643 Views

Simulation setup script is for .ip and .qsys files. The Intel® Quartus® Prime software can generate a msim_setup.tcl simulation setup script for IP cores in your design. The script compiles the required device library models, compiles the design files, and elaborates the design with or without simulator optimization. Refer https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/modelsim-simulation-setup-script-example.html and https://www.youtube.com/watch?v=eviC0jP90ZA. Generate Simulation Setup Script for IP feature only in pro version.

DO file (simulation without nativelink) for executing several simulation commands like mapping library, source setup script, compile design files, add wave, vsim and etc. VO file

VO file is a functional netlist file. Refer https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/functional-results-simulate-the-ddr.html and https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/simulating-the-shift-clk-design-in-the.html simulation design examples.

For your case, I think you still need to create a testbench file to simulate the design. Can either simulate with nativelink or without nativelink.


Thanks,

Best Regards,

Sheng


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ShengN_Intel
Employee
632 Views

Hi,


Any further update or concern for this thread?


Thanks,

Best Regards,

Sheng


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ShengN_Intel
Employee
618 Views

Hi,


Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.


Thanks,

Best Regards,

Sheng


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