Getting errors when I run analysis and elaboration.

[bteddy]

Hello,

I have a verilog file "10ustep_stepperdriver.v" attached.

Using Quartus II 64-bit ver.13.1 web edition.

I was trying to run analysis and elaboration to get a RTL netlist (schematic).

I get an error:

Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(45): created implicit net for "G14"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(49): created implicit net for "G24"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(49): created implicit net for "Q12"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(62): created implicit net for "G16"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(62): created implicit net for "Q02"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(63): created implicit net for "Q03"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(64): created implicit net for "Q04"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(65): created implicit net for "Q05"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(68): created implicit net for "G13"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(68): created implicit net for "G15"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(69): created implicit net for "G18"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(71): created implicit net for "G12"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(73): created implicit net for "G11"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(77): created implicit net for "G17"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "G00"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "G05"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "Q00"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(84): created implicit net for "G10"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(84): created implicit net for "Q01"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(86): created implicit net for "G100"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(87): created implicit net for "G101"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(88): created implicit net for "G102"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(89): created implicit net for "G103"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(90): created implicit net for "G104"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(91): created implicit net for "G105"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(92): created implicit net for "G106"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(93): created implicit net for "G107"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(94): created implicit net for "G108"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(95): created implicit net for "G109"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(98): created implicit net for "G110"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(99): created implicit net for "G111"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(100): created implicit net for "G112"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(101): created implicit net for "G113"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(102): created implicit net for "G114"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(103): created implicit net for "G115"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(104): created implicit net for "G116"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(105): created implicit net for "G117"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(106): created implicit net for "G118"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(107): created implicit net for "G119"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(120): created implicit net for "G20"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(120): created implicit net for "G19"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(122): created implicit net for "G21"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(122): created implicit net for "Q10"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(130): created implicit net for "G22"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(130): created implicit net for "G19B"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(132): created implicit net for "G23"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(132): created implicit net for "Q11"
Error (12007): Top-level design entity "10ustep" is undefined
Error: Quartus II 64-Bit Analysis & Elaboration was unsuccessful. 1 error, 47 warnings
Error: Peak virtual memory: 437 megabytes
Error: Processing ended: Tue Jul 26 15:08:44 2022
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02

What is wrong? How do I fix it.

Thank You

[sstrell]

You're getting all those warnings because you are defining a whole bunch of signals without creating signal (wire) declarations.

The error is most likely because you've named the top-level entity in your Quartus project 10ustep, but the module name in this code is DRV_10uSTP.  Change the code or change the name of the top-level entity for the project.

[bteddy]

thanks for the reply.

Not my code.

Came from another board, can't find author.

So, I should named the top-level entity in project 10ustep, and the module name should be the same "10ustep"?

How do I get it to create the schematic so I can do the wires?

[sstrell]

Yes, the top-level entity name must match.  Just select "Set as top-level entity" from the Project menu with this file open in Quartus.

As for your second question, I'm not talking about a schematic.  This is Verilog code and you need "wire" signal declarations for all named signals in the design like you have for QA, QB, QC, and QD.

[hareesh]

Hi @bteddy ,

first thing your module name and top level entity in your project both are different.  you need to change that.

second thing in your code you have not declare so many of signals. because of that you are getting those warnings. those are marked in bellow attachment.

Thanks,