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Valued Contributor III
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Getting started with Intel HLS tools [newbie]

Hello, world!

 

I am a student working on my thesis. I am in the stage of knowing my tools and Intel HLS compiler is one of them. I know some things about Verilog HDL and some basic use of ModelSim and Quartus.

I have set up a Windows 10 computer to work with. I have installed the required software, Microsoft Visual Studio 2010, ModelSim Intel FPGA Starter Edition 10.5b and Quartus Prime 17.1 Lite Edition.

 

Following the Intel High Level Synthesis (HLS) Compiler Getting Started Guide, I ran the init_hls.bat in C:\intelFPGA_lite\17.1\hls and set up the environmental variables.

Next I have tried to compile and simulate the counter example. see attached

 

Now I need to simulate the component in ModelSim.

Can someone help me with step-by-step instructions on how to run simulation 

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Valued Contributor III
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Hi, 

 

1.Run: i++ -march="Arria10" counter.cpp command to generate a.prj folder in your directory. 

2.And open vsim.wlf from a.prj/verification directory to view the waveform. 

 

Refer the link section 6 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/hls/ug-hls.pdf 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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--- Quote Start ---  

Hi, 

 

1.Run: i++ -march="Arria10" counter.cpp command to generate a.prj folder in your directory. 

2.And open vsim.wlf from a.prj/verification directory to view the waveform. 

 

Refer the link section 6 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/hls/ug-hls.pdf 

 

--- Quote End ---  

 

 

Here are my results: 

C:\intelFPGA_lite\17.1\hls\examples\counter>i++ -march="Arria10" counter.cpp a.exe : warning LNK4088: image being generated due to /FORCE option; image may not run  

 

There is no vsim.wlf in a.prj/verification directory. 

 

The contents of verification are these: 

 

\---verification | compile.cmd | modelsim.ini | tb.qsys | tb.sopcinfo | \---tb | tb.cmp | tb.csv | tb.html | tb.sip | tb.spd | tb_generation.rpt | +---altera_irq_mapper_171 | \---sim | tb_altera_irq_mapper_171_dsk4veq.sv | +---avalon_concatenate_singlebit_conduits_10 | \---sim | tb_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv | +---avalon_conduit_fanout_10 | \---sim | tb_avalon_conduit_fanout_10_wcpjniy.sv | +---avalon_split_multibit_conduit_10 | \---sim | tb_avalon_split_multibit_conduit_10_dlmo3na.sv | +---count_10 | \---sim | tb_count_10_sa5e6hy.v | +---count_internal_10 | \---sim | | | | +---hls_sim_clock_reset_10 | \---sim | hls_sim_clock_reset.sv | +---hls_sim_component_dpi_controller_10 | \---sim | hls_sim_component_dpi_controller.sv | hls_sim_stream_sink_dpi_bfm.sv | hls_sim_stream_source_dpi_bfm.sv | +---hls_sim_main_dpi_controller_10 | \---sim | hls_sim_main_dpi_controller.sv | \---sim | tb.v | +---aldec | rivierapro_setup.tcl | +---cadence | | cds.lib | | hdl.var | | ncsim_setup.sh | | | \---cds_libs | tb_altera_irq_mapper_171.cds.lib | tb_avalon_concatenate_singlebit_conduits_10.cds.lib | tb_avalon_conduit_fanout_10.cds.lib | tb_avalon_split_multibit_conduit_10.cds.lib | tb_count_10.cds.lib | tb_count_internal_10.cds.lib | tb_hls_sim_clock_reset_10.cds.lib | tb_hls_sim_component_dpi_controller_10.cds.lib | tb_hls_sim_main_dpi_controller_10.cds.lib | +---mentor | | msim_compile.tcl | | msim_run.tcl | | msim_setup.tcl | | | \---libraries | | _info | | | +---tb_altera_irq_mapper_171 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_avalon_concatenate_singlebit_conduits_10 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_avalon_conduit_fanout_10 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_avalon_split_multibit_conduit_10 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_count_10 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_count_internal_10 | | _info | | _lib.qdb | | _lib1_0.qdb | | _lib1_0.qpg | | _lib1_0.qtl | | _vmake | | | +---tb_hls_sim_clock_reset_10 | | | _info | | | _lib.qdb | | | _lib1_0.qdb | | | _lib1_0.qpg | | | _lib1_0.qtl | | | _vmake | | | | | \---_dpi | | dpi.tfdb | | | +---tb_hls_sim_component_dpi_controller_10 | | | _info | | | _lib.qdb | | | _lib1_0.qdb | | | _lib1_0.qpg | | | _lib1_0.qtl | | | _vmake | | | | | \---_dpi | | dpi.tfdb | | | +---tb_hls_sim_main_dpi_controller_10 | | | _info | | | _lib.qdb | | | _lib1_0.qdb | | | _lib1_0.qpg | | | _lib1_0.qtl | | | _vmake | | | | | \---_dpi | | dpi.tfdb | | | \---work | _info | _lib.qdb | _lib1_0.qdb | _lib1_0.qpg | _lib1_0.qtl | _vmake | \---synopsys \---vcsmx synopsys_sim.setup vcsmx_setup.sh  

 

When I try to enable signal logging in the simulator with i++ -march="arria10" -gvhdl counter.cpp, I get the following error: 

C:\intelFPGA_lite\17.1\hls\examples\counter>i++ -march="Arria10" -gvhdl counter.cpp EmitRawText called on an MCStreamer that doesn't support it, something must not be fully mc'ized aocl-clang: error: clang frontend command failed with exit code 3 (use -v to see invocation) HLS Clang (Generating testbench object file) FAILED.  

 

Any ideas on what could be wrong :confused:
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Valued Contributor III
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Hi, 

 

Try with command : i++ -march="Arria 10" -ghdl counter.cpp 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
45 Views

 

--- Quote Start ---  

Hi, 

 

Try with command : i++ -march="Arria 10" -ghdl counter.cpp 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

 

When I try this: i++ -march="arria10" -gvhdl counter.cpp, I get the following error: 

C:\intelFPGA_lite\17.1\hls\examples\counter>i++ -march="Arria10" -gvhdl counter.cpp EmitRawText called on an MCStreamer that doesn't support it, something must not be fully mc'ized aocl-clang: error: clang frontend command failed with exit code 3 (use -v to see invocation) HLS Clang (Generating testbench object file) FAILED.
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Valued Contributor III
45 Views

Hi, 

 

Apologies for the late response. 

Try with Quartus std or pro edition. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Employee
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-gvhdl is wrong option... correct switch is -ghdl ... no 'v'.

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