Thank you for taking time to read my post.
I am using Quartus PRO 18.1, with verilog HDL. I would like to understand how Quartus uses the declarative statements. I have a file, features.vh, which contains a list of directives that I use to include certain modules in my code. I would like to to declare these directives at the top module and have them also be declared for all other modules. I suppose my goal is to determine how to define global directives (if there is such a thing).
My top level module contains:
and my features.vh contains:
For my top level module, everything works as expected, however for other modules, the USE_THIS, and USE_THIS2 are not declared. If for all modules I include `include "features.vh" , then I can use USE_THIS, and USE_THIS2 for those respective modules. Is there a way to declare the global directives?
Thank you for all of your help.
As far as I know there isn't a way to have global directives. You'll have to add `include "features.vh" to all the modules using the features.vh header file.
Thank you for your reply.
It looks like having, `include "features.vh" at the top of each of my modules is one solution.
I also noticed that in Quartus > assignments > settings > Verilog HDL input and add MACRO =1 will add the following to the QSF:
set_global_assignment -name VERILOG_MACRO "MYMACRO=1"
which will allow directives to engage in all modules.
Thanks for sharing your solution. With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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