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Altera_Forum
Honored Contributor I
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HDL OPenCL issue (Avalon ST Interface Issues)

Hi, 

Please can someone did work with HDL and OpenCL (Avalon ST interface). 

I did a very simple project with HDL-kernel Co-design like the first advanced example in altera design examples. And my question is about valid and ready signal in Avalon interface ? I force valid signal to 0. When valid signal is 0 it suppose no valid data is being to be transfered. 

What I did, I tried to print with printf fonction the data transfered from HDL module to kernel when valid is 0 and the problem I have exactly the same data transfered.  

My data is always transfered from HDL to Kernel and it doesn't matter when valid signal is 0 (invalid data) or 1 (valid data) !!! 

I don't know how to fix it ? What happens with Avalon interface when valid Signal is 0 ? 

Thank you.
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Altera_Forum
Honored Contributor I
31 Views

I see this post is an exact duplicate of http://alteraforum.com/forum/showthread.php?t=58309. Please respond there so we don't get a split thread.

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