HDL with Quartus 10.0 (state machines and counters)

[Altera_Forum]

Hi Forum, 

 I am not sure if this the right forum. I am working in a project in which part of the code was written in HDL. There is a state machine, SM, which changes states according to some counters. The counters are defined as DFFs. I have found that the counters reset themselves when changing states. I had to use statements like counter[].clrn=VCC to avoid counter to be reseted. I have used one of the states of the SM to clock the counter (counter[].clk= (State_machine==STATE3)). I have found very difficult to predict when the counter will add.  Would anybody with experience coding in HDL give me some advice?  Regards, Cabrera

[Altera_Forum]

That sounds like AHDL, which is a depricated language. You cannot simulate it so debugging is harder. It also has some quirks you need to be aware of. You would be better off using either VHDL or verilog, as you can simulate them in modelsim, which makes debugging a whole lot easier., 

 Could you post the code and specific problems as we may be able to help.

[Altera_Forum]

--- Quote Start ---  I have used one of the states of the SM to clock the counter (counter[].clk= (State_machine==STATE3)).  --- Quote End ---   That's definitely not a good way to design a FSM. All FFs holding the state variable and additional information should be clocked by a single system clock.