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HPS -> FPGA Throughtput Experiment

james57
New Contributor I
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Hi all,

 

I am attempting an experiment to calculate the throughput of the HPS -> FPGA Bridge and the Visa-versa on the Stratix 10. I decided that I would use a FIFO in Quartus Platform Designer to accomplish this, essentially writing to the FIFO from HPS until the FIFO is full and time the process from the first to last write on software. This would give me a time elapsed and a known number of bits to calculate the throughput. The same concept would be applied on the way back.

 

After designing a simple Qsys design using the Avalon FIFO Memory IP I noticed in the documentation given API for the IP core.

 

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/intel-fpga-avalon-fifo-memory-api.html

 

I then looked into how as it would streamline to software process. I noticed that the fucntions required two header files - 

<altera_avalon_fifo_regs.h>, <altera_avalon_fifo_utils.h>

which were located at <install_dir>\quartus\sopc_builder\components\altera_avalon_fifo\HAL\inc\ ...

but when I checked this location this directory did not exist from the components folder on.

Maybe I am looking at older documentation but it foiled my plans of using the APIs.

 

How come I am missing this directory? Or if it is easier, how could I test the throughput in a different way? Any help on completing this experiment helps.

 

Thanks,

 

James

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11 Replies
EBERLAZARE_I_Intel
971 Views

Hi,


Let me check this on my side.


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EBERLAZARE_I_Intel
922 Views

Hi,


What is your machine environment? Linux or Windows, if so which version?


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james57
New Contributor I
904 Views

Hi @EBERLAZARE_I_Intel 

 

Linux Ubuntu 22.04.2 LTS

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EBERLAZARE_I_Intel
846 Views

Hi,


I am still checking if our GHRD have this feature or anything related, I shall get back to you.


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james57
New Contributor I
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EBERLAZARE_I_Intel
777 Views

Hi,


I am still checking on the examples, we have for FPGA to HPS bridge example, HPS sets data on memory and then it is retrieved form the FPGA through mSGDMA.


We have a documentation on the bridges, but for Agilex SoC:

https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilex


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james57
New Contributor I
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Hi @EBERLAZARE_I_Intel 

 

I have looked through the documentation and am unable to find a solid number.

Could an estimation of the throughput for the HPS <-> FPGA bridge and F->S bridge be made?

I have been able to calculate from a design but am unsure if I am correct.

 

Thanks,

James

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EBERLAZARE_I_Intel
716 Views

Hi,


We do not have the actual numbers for the throughput as it would varies from design and the HPS load itself.


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EBERLAZARE_I_Intel
716 Views

Hi,


We do not have the actual numbers for the throughput as it would varies from design and the HPS load itself.



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EBERLAZARE_I_Intel
681 Views

Hi,


Do you have any other questions?


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EBERLAZARE_I_Intel
658 Views

Hi,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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