Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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HPS unused IO Access on Arria 10

BTanner
Beginner
489 Views

I can add .gpio_x_pad_out_export and .gpio_din_export to HPS Sys, but the Interface Planner only allows pin selection for the Bank 2L GPIO1_IO23..0. It doesn't allow selection of the unused pins of GPIO0_IO11..4. These are unused HPS I/O and need to be assigned to .gpio_x_pad_in & out _export. How is this enabled? Why is unused GPIO1 allowed and not unused GPIO0?

Other pins in Bank 2L GPIO0 are used, with the pin multiplexer, for USB1 and UART0. The reset of the pins are not used.

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1 Solution
EBERLAZARE_I_Intel
291 Views

Hi,


I understand now, however in your case, in the documentation stated that:


There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.


In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.


So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.


Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html


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13 Replies
sstrell
Honored Contributor III
439 Views

Can you show your configuration in the HPS parameter editor?

EBERLAZARE_I_Intel
434 Views

Hi,


Yes, can you share your HPS parameter editor, or share your qsys file.


BTanner
Beginner
413 Views

Attached is a doc with images of the HPS parameter editor and the schematic bank with the shared I/O. The zip file contains the qsf file for the project.

BTanner
Beginner
413 Views

Here is the qsys file.

EBERLAZARE_I_Intel
396 Views

Hi,


Thanks for the files and screenshot.


However, it seems I have issue to look at your qsys file, is it possible that you archive your project.


And also, screenshot your "Arria 10 HPS" Parameters Settings.


BTanner
Beginner
389 Views

Thanks for the help.

Here is the project and screen shots of the various Parameter Tabs.

sstrell
Honored Contributor III
379 Views

If you want finer control of the HPS pin usage, go to the Advanced Pin Placement tab in the parameter editor as seen in your screenshot.  By just enabling the peripherals you want like you have, you have no control over their placement.

BTanner
Beginner
368 Views

Thanks for that input. I understand about the fixe placement of the HPS peripherals. It is the unused ones, that are free to connect to the FPGA fabric. It is these unused ones where the Interface Planner only allows the placement of these in the GPIO1 pins of the 2L bank and not the GPIO0. The unused (by the HPS) pins of the entire 2L bank are supposed to be assignable to the fpga fabric.

sstrell
Honored Contributor III
361 Views

So you're talking about "loaner I/O", allowing the FPGA to use HPS pins.  Did you check the Advanced FPGA Placement tab?

EBERLAZARE_I_Intel
325 Views

Hi,


Any update from your side?


The settings are in the Advanced Pin Placement tabs, in the HPS parameters in the screenshot if you can see. Open that, and set to the GPIO "pin name".


BTanner
Beginner
309 Views

I believe, and it matches with the behavior of Quartus’ Interface Planner, that to assign unused HPS GPIO, from the 2L bank, for connection to the fabric (not HPS) you add the GPIO Intel FPGA IP (they no longer use the term Loaner I/O).

This will provide an I/O connection to the I/O pad and an interface for the FPGA Fabric.

BTanner_1-1649819876361.png

 

BTanner_2-1649819876364.png

The Interface Planner will allow placement of the pad_in/out only in the Q3 & Q4 I/Os of the 2L bank. It is supposed to allow placement of them in the unused pins of the Q1 & Q2 pins.

The selection of the GPIO in the IP selection on the Advanced Pin Placement, assigns an IO pin to the HPS and not a connection to the fabric.

BTanner_0-1649819842574.png

 

EBERLAZARE_I_Intel
292 Views

Hi,


I understand now, however in your case, in the documentation stated that:


There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.


In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.


So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.


Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html


BTanner
Beginner
277 Views

Thank you for the explanation and details.

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