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KJOSH5
Beginner
265 Views

Hello, I am a beginner in using Quartus lite 18.0 edition. I am facing issue with running the functional stimulation after designing my circuit in verilog . I get 0 errors and zero warnings,but it still shows EDA Netlist Writer Unsuccessful.

 Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details.

Info: Processing started: Sun Jun 09 22:33:29 2019

Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=on light -c light --vector_source=C:/Desktop/introtutorial2/Waveform.vwf --testbench_file=C:/Desktop/introtutorial2/simulation/qsim

Error: Quartus Prime EDA Netlist Writer was unsuccessful. 0 errors, 0 warnings

Error: Peak virtual memory: 4722 megabytes

Error: Processing ended: Sun Jun 09 22:33:32 2019

Error: Elapsed time: 00:00:03

Error: Total CPU time (on all processors): 00:00:02

 

Error. 

0 Kudos
3 Replies
41 Views

Is the EDA Tool properly setup? Go to Tools -> Options -> EDA Tool Options and set the ModelSim-Altera directory.

example directory: C:\intelFPGA\18.1\modelsim_ase\win32aloem

 

Sharing your design might help with further understanding.

KJOSH5
Beginner
41 Views

Hello,

Thanks for the response . I have tried the suggested solution but it did not work.

Following is my design code

module light(x1,x2,f);

    input x1,x2;

output f;

assign f=(x1 & ~x2)|(~x1 & x2);

endmodule

 

I am not able to run the functional simulation for the above code.

Kindly advise.

 

 

41 Views

Your design works though. Is the EDA Tool Settings > Simulation > Tool Name, is set as ModelSim-Altera?

Or you can try the steps by steps guidance with below link and check whether the same issue occur again.

 

http://www.swarthmore.edu/NatSci/echeeve1/Ref/embedRes/QQS_V/QuickQuartusVerilog.html

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