Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
1,940 Views

Hello, I am new to Altera and Quartus and I needed help. I'm using Altera EPM3032ATC44-10 on my hardware development board. I have Quartus II 13.0.

Hello,

I am new to Altera and Quartus and I needed help. I'm using Altera EPM3032ATC44-10 on my hardware development board. I have Quartus II 13.0. 

 

I wrote a code in VHDL for one of my company's projects. It was an add-on to one of our existing codes with not a lot of changes to it. It compiles without errors but I see very abrupt and unexpected outputs on my development board. I wanted to know if, if I make any changes to the source code, should I be modifying any other files in it too? Because I,m observing weird outputs when I make even minor changes to the code.

 

2- Are we supposed to use the .pof file generated to program my CPLD on the development board?

 

3- How critical is the .sdc file? Is it mandatory to write one? 

 

Any help will be appreciated. Thanks

Tags (1)
0 Kudos
6 Replies
Highlighted
New Contributor II
2 Views

Hello,

 

Welcome to the forum.

 

First step, if I had your challenge, would be to compile the existing code and download it.

It would not be the first time someone starts with a bad version and then wonders where the problems came from.

Completing this step would mean that you have the download and compile process under control.

 

Quartus generates several types of downloadable output files. .Sof & .Pof are 2 of them. .sof = directly downloadable to your fpga, but volatile, .pof = files made for non volatile memory.

Typically you download .sof during development and then, when all is ok, you convert .sof to .pof and download this to some kind of non volatile memory.

 

.sdc is Quartus info to get timing constraints right. In principle you need this file to get things right.

However, in simple projects with timing constraints that are not critical, you can get your project working without worrying too much about this.

A basic version can be sufficient.

All depends on the complexity and timing of what you are doing.

 

Best Regards,

Johi.

0 Kudos
Highlighted
Valued Contributor I
2 Views

I have a design based on an Altera/Intel EPM3064ALC44-7, so it very similar to yours.

 

You will use the .pof files to program CPLD devices.

 

An .sdc file for a CPLD can usually be pretty simple. For my device I use this:

 

# Input 20MHz reference clock create_clock -period 50.0 -name CLK [get_ports {CLK}]   # Input delays set_input_delay -clock CLK -max 4.0 [all_inputs] set_input_delay -clock CLK -min 1.0 [all_inputs]   # Output delays set_output_delay -clock CLK -max 4.0 [all_outputs] set_output_delay -clock CLK -min 1.0 [all_outputs]

That's it for the .sdc file. I use Quartus 13.0sp1.

 

Do you run your code thru a simulation testbench? I highly recommend it, it will save a lot of headaches like you are seeing.

0 Kudos
Highlighted
Beginner
2 Views

Thanks. I'll start with the original code

0 Kudos
Highlighted
Beginner
2 Views

Thanks. Is that all for the .sdc file? I have been trying doing simulations too but the outputs on the simulation are different from what I am seeing in reality.

0 Kudos
Highlighted
Valued Contributor I
2 Views

That is just about a bare minimum .sdc configutation for the clock, input, and output timing.

 

When you compile, does the Quartus timing analyzer indicate any timing errors?

 

Do you have a simpler source design file you can use to simulate and then verify in your hardware?

 

Do you know your hardware board is operating without error? Do you have another board to try and see if the behavior is the same?

0 Kudos
Highlighted
Beginner
2 Views

The timing analyzer does not give me an error, but I get a warning which says .sdc file is missing. The code gets compiled just fine.

There is no issue with the hardware board since we are writing a new source code (modified from the original source code with minor modifications) on the old hardware which works fine.

0 Kudos