Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15332 Discussions

Hello, I am using a Altera Stratix® V GX FPGA (5SGXEA7N2F45C2). The default clock frequency is 50MHz. I am using the pin PIN_AW35. Can I change the clock frequency? What is the maximum limit? Thanks

ASubr1
Beginner
985 Views
0 Kudos
2 Replies
Rahul_S_Intel1
Employee
102 Views

Hi,

The maximum frequency supported by an IO pin is not available data sheet, the pin that is mentioned is the IO clock pin. If you are using the PLL in that PIN the maximum frequency 800Mhz, otherwise have to do the simulation.

 

Regards,

RS

ASubr1
Beginner
102 Views

Thank You.

Reply