Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Hello, I have a DE10-Lite board that I am trying to convert BCD to Decimal. Hear is my code and I am having issues getting is to work, can you see where I'm going wrong?

KRose13
Beginner
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//////////////////// BCD TO DECIMAL //////////////////////////////

 

module DE10_LITE_Default( input [1:0]KEY,

input [9:0]SW,input CLK,

output [9:0]LED,

output [7:0]HEX_0,output [7:0]HEX_1, output [6:0]HEX_2, output [6:0]HEX_3); // HEXOUT_0

reg [3:0]module_select;

wire [7:0]add_out;

wire [9:0]math_carry;

Arithmetic math_block(SW[9:8],SW[7:0],math_carry[9],add_out[7:0]);

wire [9:0]logical_out;

Logical logic_block(SW[9:8],SW[7:0],logical_out[7:0]);

wire [3:0]compare_out;

Comparison compare_block(SW[9:8],SW[7:0],compare_out[3:0]);

wire [9:0]soultion_output;

solution(CLK, soultion_output[9:0]);

//display what the sub-module selection is on HEX_2

SevenSegment HEX2({1'b0,1'b0,SW[9],SW[8]},HEX_2[6:0]); // HEXOUT_2

//display what module number the user is in on HEX_3

SevenSegment HEX3(module_select[3:0],HEX_3[6:0]); // HEXOUT_3

//Use the first button to cycle one way through the different modules

always@(posedge KEY[0],posedge KEY[1])

begin

module_select = (module_select + 1) % 4;

end

//use multiplexors to switch between the different outputs on the first two HEX displays depending on the module selection

wire [3:0]HEX0_in;

MUX HEX0_MUX({4'b0000,compare_out[3:0],logical_out[3:0],add_out[3:0]},module_select[1:0],HEX0_in[3:0]);

defparam HEX0_MUX.n = 4;

SevenSegment HEX0(HEX0_in[3:0],HEX_0[6:0]); // HEXOUT_0

wire [3:0]HEX1_in;

MUX HEX1_MUX({4'b0000,4'b0000,logical_out[7:4],add_out[7:4]},module_select[1:0],HEX1_in[3:0]);

defparam HEX1_MUX.n = 4;

SevenSegment HEX1(HEX1_in[3:0],HEX_1[6:0]); // HEXOUT_1

//if the processor is in arithmetic mode, have the most significant decimal point match the multiplication carry,

//and least significant match the division carry

assign HEX_0[7] = ~(~module_select[0] & ~module_select[1] & SW[9] & SW[8] & math_carry[9]);

assign HEX_1[7] = ~(~module_select[0] & ~module_select[1] & SW[9] & ~SW[8] & math_carry[9]);

//use a 10 bit multiplexor to switch between the different outputs of the LEDs depending on the module selection

MUX LED_MUX({solution_output[9:0],10'b0000000000,logical_out[9:0],math_carry[9:0]},module_select[1:0],LED[9:0]);

defparam LED_MUX.n = 10;

endmodule

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sstrell
Honored Contributor III
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What is not working correctly? What exactly are you expecting? What have you tested? What is the code for the instantiated modules? Are you getting error messages?

 

More detail needed here.

 

#iwork4intel

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SyafieqS
Moderator
554 Views

Hi Kassy,

What are you expecting from thee design? Is there any error message you could provide?

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