The 100MHz clock is clocking I/O and generating time delays in the logic circuit. I have used the Timing Analyzer and SDC file to constrain the clock, as well as the I/O, however I am getting errors with failed timing paths. See attached for the top failing paths from Timing Analyzer.
If I change my clock to 50MHz, I then have no failing paths. However, a 100MHz clock is favourable for my application. My question is, is there a way I can optimise my timing paths so that I can still use a 100MHz clock without timing failures, or is this a limitation which can't be worked around without changing the CPLD or my logic circuit?
Just from that timing report, you have a huge amount of clock skew, almost 5 ns, between the sources and destinations of the failing paths. How is your clocking set up? Have you gated your clocks for some reason?
An update - I have optimised my logic circuit design. I still get timing path failures when using a 100MHz clock, yet a 50MHz clock has zero failed timing paths. However, I now have zero clock skew. See attached my new failing paths in Timing Analyser and new logic circuit (which is again repeated 6 times, with a shared clock).
Any help rectifying my timing path failures for a 100MHz clock would be greatly appreciated.
Well, now instead of large clock skew, you have large data path delays. What did you change in your design? Why are you using the data signal as the clrn control on the registers? The large fanout there could be the problem now.
I removed the clocks from all inputs and outputs, as they were not required and actually causing application issues. And I introduced a second timer on each of the 6 sub-circuits, as using one single timer was also causing application issues. I am using the data signal as the clrn control for the flip-flops as again, for my application, I would like to clear them when this signal is low - is this how this function is intended to be used?
I've experimented with disconnecting the clock signal from some of the flip-flops in order to play with the fanout. Although the number of flip-flops connected to the clock signal did change the slack, there was no correlation between the fanout number and the amount of slack - ie. reducing the fanout didn't necessarily reduce the negative slack and increasing fanout didn't necessarily increase negative slack.
No, clrn is for resetting a register. It is typically only used at reset time and used with a separate reset signal that goes low at reset time and then is held high during normal operation. D flip flops are cleared during normal operation by the D input being low at a clock toggling edge (positive or negative edge depending on the flip flop).
And as I stated, the fan-out of the data/clrn signal may be an issue now, not the clock signal, so I'm not sure I understand your second paragraph.
Can you also clarify exactly which paths are failing timing? It's difficult to correlate your timing report with the tiny text on the schematic.
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