Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen similar connection of the epcs flash controller in some examples.
I get no setup time violations and functionally everything works fine. But I can't get rid of hold time violation warnings. See the attached TimeQuest Report. Please help.
Hi @KhaiY_Intel ,
I haven't solved it yet. Not really clear how to overconstrain the hold warnings of the same clock To and From the same signal. The number of the warnings (I could see a few hundreds of them and don't know the exact number - could be much higher) makes me think that something basic is wrong.
I've tried to remove the .sdc file and leave only derive_pll_clocks, but this type of warnings still appears, so it is not the .sdc file issue.
I'm working with Quartus 16.1, someone advised me to try a newer version. I can try it on the next week.
If you have any new ideas, I'll appreciate it.