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- Help - Creating alarm clock with modulo counter - System verilog

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Altera_Forum

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11-30-2017
03:52 PM

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Help - Creating alarm clock with modulo counter - System verilog

I am trying to create an alarm clock using a Terasic CycloneV fpga. I need to be able to set the time and an alarm. Right now I'm unable to get the clock to reset at 24 hours. I have attached the modulo counter module as a .txt. Can anyone help with the statement to reset at 24 hours?

```
module testFiveBitCounter(input logic CLOCK_50,
input logic KEY,
input logic SW,
output logic LEDR,
output regHEX0,
output regHEX1,
output regHEX2,
output regHEX3,
output regHEX4,
output regHEX5);
logic oneSecondEnable, tenSecondEnable, oneMinuteEnable,
tenMinuteEnable, oneHourEnable, tenHourEnable, temp = 1'b0;
logic countSecOnes;
logic countSecTens;
logic countMinOnes;
logic countMinTens;
logic countHourOnes;
logic countHourTens;
always_ff @(posedge oneSecondEnable) begin
temp = ~temp;
LEDR = temp;
end
sevenSeg digit0(.H(HEX0), .B(countSecOnes));
defparam oneSecond.n = 26;
defparam oneSecond.k = (50000000)/75; //5000000
moduloCounter oneSecond(.clk(CLOCK_50),
.enable(1'b1),
.resetN(KEY),
.rollover(oneSecondEnable));
logic rollOnes;
defparam ones.n = 4;
defparam ones.k = 9;
moduloCounter ones(.clk(CLOCK_50), //oneSecondEnable
.resetN(KEY),
.enable(oneSecondEnable), //1'b1
.count(countSecOnes),
.rollover(rollOnes));
sevenSeg digit1(.H(HEX1), .B(countSecTens));
logic rollTens;
defparam tens.n = 3;
defparam tens.k = 5;
moduloCounter tens(.clk(CLOCK_50), //tenSecondEnable
.resetN(KEY),
.enable(oneSecondEnable & rollOnes), //1'b1
.count(countSecTens),
.rollover(rollTens));
sevenSeg digit2(.H(HEX2), .B(countMinOnes));
logic rollMinsOnes;
defparam onesMin.n = 4;
defparam onesMin.k = 9;
moduloCounter onesMin(.clk(CLOCK_50), //oneMinuteEnable
.resetN(KEY),
.enable(oneSecondEnable & rollOnes & rollTens), //1'b1
.count(countMinOnes),
.rollover(rollMinsOnes));
sevenSeg digit3(.H(HEX3), .B(countMinTens));
logic rollMinTens;
defparam tensMin.n = 3;
defparam tensMin.k = 5;
moduloCounter tensMin(.clk(CLOCK_50), //tenMinuteEnable
.resetN(KEY),
.enable(oneSecondEnable & rollOnes & rollTens & rollMinsOnes), //1'b1
.count(countMinTens),
.rollover(rollMinTens));
sevenSeg digit4(.H(HEX4), .B(countHourOnes));
logic rollHourOnes;
defparam onesHour.n = 4;//4
defparam onesHour.k = 9;//9
moduloCounter onesHour(.clk(CLOCK_50), //oneHourEnable
.resetN(KEY),
.enable(oneSecondEnable & rollOnes & rollTens & rollMinsOnes & rollMinTens), //1'b1
.count(countHourOnes),
.rollover(rollHourOnes));
sevenSeg digit5(.H(HEX5), .B(countHourTens));
logic rollHourTens;
defparam tensHour.n = 3;//4
defparam tensHour.k = 5;//5
moduloCounter tensHour(.clk(CLOCK_50), //tenHourEnable
.resetN(KEY),
.enable(oneSecondEnable & rollOnes & rollTens & rollMinsOnes & rollMinTens & rollHourOnes), //1'b1
.count(countHourTens),
.rollover(rollHourTens));
/*this is the part that doesn't work
always_ff @(posedge oneSecondEnable) begin
if (rollHourTens ==2 & rollHourOnes==4) begin
reset;
end
end
*/
endmodule
```

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5 Replies

Altera_Forum

Honored Contributor I

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11-30-2017
04:17 PM

132 Views

What problems are you having? What have you tried so far?

Altera_Forum

Honored Contributor I

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11-30-2017
04:44 PM

132 Views

Altera_Forum

Honored Contributor I

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11-30-2017
06:28 PM

132 Views

Altera_Forum

Honored Contributor I

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12-01-2017
05:58 AM

132 Views

The reason for the always_ff block not working is because you'v used the bit-wise AND (&) operator and not the logical AND (&&). Change the '&' to '&&' and try. It will trigger this time.

```
/*this is the part that doesn't work
always_ff @(posedge oneSecondEnable) begin
if (rollHourTens ==2 & rollHourOnes==4) begin <------ Change this to logical && from the bitwise &
reset;
end
end
*/
```

Altera_Forum

Honored Contributor I

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12-01-2017
06:05 PM

132 Views

--- Quote Start --- The reason for the always_ff block not working is because you'v used the bit-wise AND (&) operator and not the logical AND (&&). Change the '&' to '&&' and try. It will trigger this time.

```
/*this is the part that doesn't work
always_ff @(posedge oneSecondEnable) begin
if (rollHourTens ==2 & rollHourOnes==4) begin <------ Change this to logical && from the bitwise &
reset;
end
end
*/
```

--- Quote End --- Altho the answer is technically correct (you should syntactically be using - Subscribe to RSS Feed
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