Help:What does the TimeQuest Timing Analayzer's info mean?

[Altera_Forum]

I have read the quartusii_handbook(7.1) . I run the TimeQuest Timing Analyzer ,but i find there are not any constraints shown in the handbook, such as "check_timing", i have to write commands in the console. Do i have to learn the commands in the handbook? 

After i read SDC files i have created , i key in "check_timing" in the console, it shows the info below:  Info: Check Timing: Info: No Clock  Info: forewordelay0001:inst|freqdiv:inst|24 Node was determined to feed a clock port but was found without an associated clock assignment.   Info: databefore:inst8|inst14 No clock feeds this register's clock port.  Info: No Output Delay  Info: clk1 No output delay was set on output port.  Info: No Uncertainty  Info: clk (Rise) clk (Rise)   Info: compare4:inst1|y3 (Rise) clk (Rise)   Info: compare4:inst1|y1 (Fall) clk (Rise)   Info: datain (Rise) clk (Rise)   Info: clk (Rise) compare4:inst1|y3 (Rise)   Info: compare4:inst1|y3 (Rise) compare4:inst1|y3 (Rise)   Info: clk (Rise) compare4:inst1|y1 (Fall)   Info: compare4:inst1|y1 (Fall) compare4:inst1|y1 (Fall)   Info: clk (Rise) datain (Rise)   Info: datain (Rise) datain (Rise)   Info: clk (Rise) compare4:inst1|y2 (Rise)  Info: Summary   For the info: No output delay, i set output delay to clk1, but systerm shows:  "Warning: Ignored assignment set_output_delay  Warning: Argument -clock with value [get_clocks {clk1}] contains zero elements". What's wrong with it? For the info: no uncertainty, I'm confused by the info. What do they mean? I set the clock uncertainty with some of them , but i find the clock period changed to the global clock(clk)(They should not to be the period). In my design, compare4:inst1|y1~y3 and datain are not the real clock , i just use them to feed the dff . Do i need to set them as clock or generated clock? If it is, how to set the period or the divided parameter?  Thanks very much, everyone. Please!

[Altera_Forum]

--- Quote Start ---  ... i have to write commands in the console.  --- Quote End ---    If you can use the TimeQuest GUI commands like those in the Tasks pane, that will probably be easier for you as a new user. Anything you do in the GUI you can do at a console command line or in a script, but the GUI might be easier starting out.      --- Quote Start ---  Info: Check Timing: Info: No Clock  Info: forewordelay0001:inst|freqdiv:inst|24 Node was determined to feed a clock port but was found without an associated clock assignment.  Info: databefore:inst8|inst14 No clock feeds this register's clock port.  --- Quote End ---    This is for your ripple clock. I've mentioned http://www.alteraforum.com/forum/showthread.php?t=754 to you before, but I'll mention it again for other readers of this thread. See my posts there for cautions and guidance concerning ripple and gated clocks.  When you ran update_timing_netlist, you probably got something like this:    --- Quote Start ---  Warning: Node: forewordelay0001:inst|freqdiv:inst|24 was determined to be a clock but was found without an associated clock assignment.  --- Quote End ---    If you run "report_ucp -panel_name "Unconstrained Paths"" or double click "Tasks --> Report Unconstrained Paths" in the GUI, I expect you'll see the ripple clock listed as unconstrained.  If you are going to use a ripple clock, then you need to add or fix the create_generated_clock to constrain it. If you already tried create_generated_clock for it, then you probably got a warning for it. Look for the warning or run "report_sdc -ignored" or "Tasks --> Report Ignored Constraints" to see why the generated clock constraint was ignored. The end of your post sounds like you are asking how to create this particular generated clock. See http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html for an example of a divide-by-2 ripple clock.      --- Quote Start ---  Info: Check Timing: ... Info: No Output Delay  Info: clk1 No output delay was set on output port.  ...  For the info: No output delay, i set output delay to clk1, but systerm shows:  "Warning: Ignored assignment set_output_delay  Warning: Argument -clock with value [get_clocks {clk1}] contains zero elements". What's wrong with it?  --- Quote End ---     Is clk1 an output port (device pin) driving a clock out of the FPGA? Is it a source-synchronous output clock going to an external device with the FPGA data output ports (device pins) also going to that external device?  If clk1 is an output port being used as a clock, then "clk1" will be in the get_ports collection, but it won't be in the get_clocks collection unless you've created a clock constraint with that same "clk1" name.  If clk1 is a source-synchronous output clock, then you probably need to create a generated clock with the clk1 port as the target. The generated clock will be the -clock for the set_output_delay on the data output ports. An alternative that works in some cases is "-reference_pin [get_ports clk1]" in the set_output_delay constraints for the data output ports. See http://www.altera.com/support/examples/timequest/exm-tq-basic-source-sync.html for a simple source-synchronous example including an example for -reference_pin.  If clk1 is a source-synchronous output clock and you don't care about the tco in the FPGA for this output port, you don't need an output delay on clk1 itself. To keep it from being listed as unconstrained, you can set_false_path -to [get_ports clk1]. You might want something like "set_false_path -from [get_ports clk] -to [get_ports clk1]".      --- Quote Start ---  For the info: no uncertainty, I'm confused by the info. What do they mean? I set the clock uncertainty with some of them...  --- Quote End ---    You should use clock uncertainty settings for things like PLL jitter if you want those things fully accounted for. Not all clocks need uncertainty added, and most people don't bother even for clocks that do need it for a completely correct analysis. There is a derive_clock_uncertainty command to figure out the uncertainties for Stratix II and HardCopy II so that you don't have to come up with numbers on your own.

[Altera_Forum]

Thanks very much, Brad. 

Thank you for your twice explanation for the ripple clock for me .  I find you understand my design well . Clk1 is an output port being used as a clock in my design , it is 16-divided by clk, i use some combinational logic to control clk1 in order to make clk1 and datain synchronize , datain is steady while the phase of clk1 can change arbitrary. After reading your posts , i have realized the ripple clock is not the best choose in FPGA design. Thanks again, Brad. Good luck.