Help for generate simulator script

[dsun01]

Dear Support/Expert, 

I have the following while generate simulator script.  The original Project is from TI. after port to A10 GX dev board and update to Quartus Pro 21.3. when I run Tool-> generate simulator setup script.  I got a lot of similar error like this. 

Error: 2021.11.24.07:42:57 Error: SPD file C:/FPGA/TSW14J57_pro/copy3/ip/nios2_subsystem\nios2_subsystem.spd not found. Please generate simulation files for Platform Designer file C:/FPGA/TSW14J57_pro/copy3/ip/nios2_subsystem.qsys before generating simulator setup scripts.

then I opened the nios2_subsystem.qsys and run generate testbench system. I got the following error. 

Error: nios2_subsystem_tb.nios2_subsystem_inst.custom_mm_bridge: nios2_subsystem_inst_custom_mm_bridge_bfm.s0 (0x0..0x3fffff) is outside the master's address range (0x0..0xfffff)
Error: nios2_subsystem_tb.nios2_subsystem_inst.jesd_mm_bridge: nios2_subsystem_inst_jesd_mm_bridge_bfm.s0 (0x0..0x3fffff) is outside the master's address range (0x0..0xfffff)
Error: nios2_subsystem_tb.nios2_subsystem_inst_custom_mm_bridge_bfm.s0: Agent s0 has burstOnBurstBoundariesOnly while host custom_mm_bridge does not have it.
Error: nios2_subsystem_tb.nios2_subsystem_inst_jesd_mm_bridge_bfm.s0: Agent s0 has burstOnBurstBoundariesOnly while host jesd_mm_bridge does not have it.
Error: qsys-generate failed with exit code 3: 4 Errors, 14 Warnings
Error: Could not generate simulation scripts
Error: There were errors creating the testbench system.

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the Quartus generated nios2_subsystem.spd, even it failed creating the testbench system. 

is this nios2_subsystem.spd valid for generate simulator script?

thank you,

David

[dsun01]

Dear Quartus Support/Expert,

Continue with the last question.  will I run Tool -> Generate Simulator setup script for IP. 

I got error message like this 

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Error: 2021.11.24.21:43:31 Error: SPD file C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_dec_data_capture_0\jesd204b_dec_data_capture_0.spd not found. Please generate simulation files for IP file C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_dec_data_capture_0.ip before generating simulator setup scripts.

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I checked the directory and search path,  there is a file called jesd204b_dec_data_capture_0.ip at C:\FPGA\TSW14J57_pro\copy3\ip\ip\jesd204b

the file is there, and the Quartus Pro 21.3 can compile the project without any problem. I couldn't figure out why when I open this IP with Platform Designer, the tools complain that couldn't find it. 

seems to me that the Quartus compiler and the Platform Designer follow different library searching path. 

after click Select and Open, I got the following pop up

I hope after I execute this command will fix the problem. but I don't think I can just duplicate the same line as the command, please give some hint/instruction how to set a correct command.

Thanks you,  

David 

[dsun01]

Question Related to the same issue. 

I try to regenerate the IPs. here are the Error message for some modules.

Error: reg_ctrl_0: reg_ctrl does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Error: SPD file was not generated: C:\FPGA\TSW14J57_pro\copy3\ip\ip\jesd204b\jesd204b_reg_ctrl_0\jesd204b_reg_ctrl_0.spd
Error: Could not generate simulation scripts

in this situation, if a module .spd file couldn't be generated, then the Generate simulation setup script can't execute successfully. how can I create a simulation environment for the project?

is there a command that can exclude the modules that not supported for the spd file generation? then added to the whole project manually.

thanks,

David

[dsun01 · Accepted solution]

after few days struggle, I figured out that when edit the ip, set the simulation file as copy from the synthesize. then regenerate the ip testbench. it will solve this problem. 

thanks,

David