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15311 Discussions

Help in Verilog Code: Edge Trigger

SS5
Novice
1,014 Views

I am working with Altera Cyclone V FPGA Board.

Design Goal : I need to run counter using SOPC and NIOS

Design Process:

Using Verilog Code

  1. Generating Trigger for 500ns
  2. Generating Counter data

Help: I need to collect the counter data only at positive edge of Trigger signal (not at entire positive cycle of Trigger signal).

module Counter( input clk, // Clk: 50 Mhz input enable, input reset, output reg[31:0] Final_value, output reg trig ); reg[31:0] counter_out; reg [7:0] temp=0; wire detect; reg [31:0] counter_result; reg temp1; wire temp2; always@(posedge clk) begin if(reset) begin trig<=0; temp<=0; counter_out<=0; end else if (enable==1'b1) begin counter_out<=counter_out+1; temp<=temp+1; if(temp==25) begin temp<=0; trig<=~trig; temp1<=trig; // Generating Trigger for 500ns end end end   assign temp2=temp1&&clk; always@(posedge temp2) if(reset) counter_result<=0; else begin counter_result<=counter_result+1; // Increaming the Counter end assign detect = counter_result & ~temp1; // Positive Edge detect of Trigger always@(posedge detect) if(reset) Final_value<=0; else begin Final_value<=counter_result; end endmodule

I have tried but its not giving the correct results!

 

0 Kudos
6 Replies
KhaiChein_Y_Intel
241 Views

Hi,

 

 I need to collect the counter data only at positive edge of Trigger signal (not at entire positive cycle of Trigger signal).

 

Could you elaborate? Does counter data refer to Final value? What is Trigger in this verilog code (trig or temp 1 or temp 2) ?

 

 

SS5
Novice
241 Views

Hello,

>>Does counter_result refer to Final value? Yes, But putting counter date at an edge value of Trigger into Final value reg.

 

>>What is Trigger in this verilog code (trig or temp 1 or temp 2) ?

trig

delay trig--- temp1

 

Please refer this link for detailed explanation

https://forums.intel.com/s/question/0D50P00003yyIqR/help-writing-c-code-for-niosiistratix-ii2s60?s1o...

KhaiChein_Y_Intel
241 Views

Hi,

 

If you use posedge trig, the signal will be latched at the positive edge of the clock signal (trig) within the setup and hold window but not the entire positive cycle of the clock.

 

Thanks.

SS5
Novice
241 Views

Sorry, Whether Verilog code is right ?? Please explain me briefly

KhaiChein_Y_Intel
241 Views

Hi,

Could you help me to understand why you are using detect as the clock signal for final_value?

 

Thanks

SS5
Novice
241 Views

Thanks for your response. As i have modified my design as per my head instruction. Now i am getting the output correctly.

 

 

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