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Hi everyone
I'm just trying to use vga through de2-115 board https://eewiki.net/pages/viewpage.action?pageid=15925278 I refer to this page and it works but now I'm trying to make my own vga controller but it doesn't work I think problem is on clock but it's just a guess my monitor couldn't read signal from my code I need your help this is the top modelLIBRARY ieee;USE ieee.std_logic_1164.all;
entity VGA is
port(
CLK :IN std_LOGIC;
RED :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
GREEN :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
BLUE :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
h_sync :OUT STD_LOGIC;
v_sync :OUT STD_LOGIC;
n_sync :OUT STD_LOGIC;
n_blank :OUT STD_LOGIC;
VGACLK :OUT STD_LOGIC
);
END VGA;
ARCHITECTURE AA OF VGA IS
SIGNAL RESET : STD_LOGIC:='0';
component PLL is port (
clk_in_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
clk_out_clk : out std_logic -- clk
);
end component PLL;
COMPONENT VGA_CONTROLLER IS PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END COMPONENT;
COMPONENT HW_IMAGE_GENERATOR IS PORT(
disp_ena : IN STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
COLUmn : IN INTEGER; --row pixel coordinate
ROW : IN INTEGER;
red : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); --red magnitude output to DAC
green : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); --green magnitude output to DAC
blue : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to DAC
END COMPONENT;
SIGNAL disp_ena : STD_LOGIC;
SIGNAL row : INTEGER;
SIGNAL column : INTEGER;
SIGNAL reset_n : STD_LOGIC;
SIGNAL PIXel_clk : STD_LOGIC;
begin
VGACLK<=PIXel_clk;
U1: PLL PORT MAP ( CLK, reset_N, PIXel_clk);
u2: vga_CONTROLLER port map (pixel_clk, reset_N, h_sync, v_sync, disp_ena, COLUmn, ROW, n_blank, n_sync);
u3: hw_IMAGE_GENERATOR port map (disp_ena,COLUmn, ROW, RED,GREEN,BLUE);
end AA;
and other codes LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY hw_image_generator IS
GENERIC(
pixels_y : INTEGER := 478; --row that first color will persist until
pixels_x : INTEGER := 600); --column that first color will persist until
PORT(
disp_ena : IN STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
row : IN INTEGER; --row pixel coordinate
column : IN INTEGER;
red : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); --red magnitude output to DAC
green : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); --green magnitude output to DAC
blue : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to DAC
END hw_image_generator;
ARCHITECTURE behavior OF hw_image_generator IS
BEGIN
PROCESS(disp_ena, row, column)
BEGIN
IF(disp_ena = '1') THEN --display time
IF(row < pixels_y AND column < pixels_x) THEN
red <= (OTHERS => '0');
green <= (OTHERS => '0');
blue <= (OTHERS => '1');
ELSE
red <= (OTHERS => '1');
green <= (OTHERS => '1');
blue <= (OTHERS => '0');
END IF;
ELSE --blanking time
red <= (OTHERS => '0');
green <= (OTHERS => '0');
blue <= (OTHERS => '0');
END IF;
END PROCESS;
END behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 208; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 336; --horiztonal back porch width in pixels
h_pixels : INTEGER := 1920; --horiztonal display width in pixels
h_fp : INTEGER := 128; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 3; --vertical sync pulse width in rows
v_bp : INTEGER := 38; --vertical back porch width in rows
v_pixels : INTEGER := 1200; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= 0; --reset column pixel coordinate
row <= 0; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count >= h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count >= v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior;
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3 Replies
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Have you written a testbench for this? then you can verify the timing of your signals.
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I've never made testbench before. Would you mind if I ask you to explain how to do that?
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there are many tutorials out there that go through the testbench process that would explain it better than a forum post. Some even provided by altera.
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