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Valued Contributor III
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## Help with this code

Hi, I've written a verilog code for a function that finds root by bisection method but unfortunately it's not giving the right output,maybe because of choice of variable. Can anyone please help me out with this & let me know where I did wrong? I would really appreciate it!

The code & output is attached here.

Code:

module FT_1();

reg[32:0] upper;

reg[16:0] lower;

reg[16:0] root;

initial

begin

upper=3;

lower=0;

root= apu(upper,lower);

//\$display("The root is: %f",root);

end

function[32:0] apu;

input[16:0] xu;

input[16:0] xl;

real xm;

integer i;

begin

for(i=0;i<=20;i=i+1)

begin

xm= (xu+xl)/2.0;

//apu=(xu+xl)/2.0;

if(((xm*xm)-2)<0)

begin

xl=xm;

end

else

begin

xu=xm;

end

apu=(xu+xl)/2.0;

\$display("the root is= %f" ,xm);

end

end

endfunction

endmodule

Output:

# the root is= 1.500000# the root is= 1.000000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000# the root is= 1.500000
Tags (1)
I'm not a Verilog expert, but when you do ```xl=xm; xu=xm;```You convert xm to integers, as xl and xu are integers. I assume this isn't what you wanted.