Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Hi, Every I/O Bank in arria10 FPGA has only one I/O PLL in it. Can we use the same I/O PLL for all LVDS Serdes I/O channels in the same bank without using external I/O PLL IP? OR only one LVDS channel can use the I/O PLL provided in the particular bank?

RShan23
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