Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16848 Discussions

Hi, It is posible to suppress DRC rule in Design Assistant for certain signal or design unit?

JDrba
Beginner
‎01-23-2020 04:08 PM
582 Views

For example for rule ACD-30023 when I know clock crossing between registers in_reg_12345 and out_reg_12345 is ok and I dont want to see this vialotion in report

0 Kudos

Link Copied

1 Reply
MEIYAN_L_Intel
Employee
‎01-30-2020 05:48 AM
456 Views

Hi,

 

You can customize the design assistant for your design and report requirement by spcify the options that control the rules and parameters apply to various stage of design for DRC as below with steps below:

Click Assignments > Settings > Design Assistant Rule Settings, then search the rule name (eg: ACD-30023)

For more information, you may need to refer to Chapter 2.3 as link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf

 

Thanks

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.