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High Speed Reed solomon intel FPGA IP

Rk_Athram
New Contributor I
‎02-03-2023 02:13 AM
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Hello,

I am using High speed reed solomon Intel FPGA IP and simulating using model sim for the polynomial 1033 and parallelism of 2 with each symbol being 10bits. I would like to know how do i verify the parity values/check symbols generated from the IP

 

thank you

RK

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ZiYing_Intel
Employee
‎02-07-2023 05:39 PM
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Hi RK,


Thanks for submitting the issue. Please do allow me have some time to look into your issue and I will get back to you with findings.


Best regards,

Zi Ying


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ZiYing_Intel
Employee
‎02-07-2023 11:14 PM
702 Views

Hi RK,

 

You may check whether the value is a legal value through the table of parameters, Table 11, pg 23,

 

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ZiYing_Intel
Employee
‎02-09-2023 06:40 AM
693 Views

Hi RK,


Since I have addressed your question and haven't hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.


Best regards,

Zi Ying


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