Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16592 Discussions

Host Channel Support for 17.0

Altera_Forum
Honored Contributor II
1,348 Views

Best I can gather, there should be support for host/FPGA channels as of 17.0 for cross communication. I cannot, however find any documentation on them, most importantly how to implement them from both sides. Is there support, and if so, where can I find documentation on how to implement it?

0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
399 Views

I opened a service request with Altera regarding the exact same thing a few weeks ago. What I was told is that support for host channels is only available in a specific BSP for Altera's reference Arria 10 board, and this BSP is not available to public yet.

0 Kudos
Altera_Forum
Honored Contributor II
399 Views

Given no channel support, what is the prescribed method of shunting data across the PCI in such a manner as the host can detect (or be alerted) when the FPGA has passed (or wants to pass) information across without calling the kernel's return?

0 Kudos
Altera_Forum
Honored Contributor II
399 Views

You can check OpenCL's clEnqueueMapBuffer() function and/or the concept of host pointers in OpenCL to see if they serve your purpose. I am not sure how much these are supported by Altera (Altera's documents detail what is supported and what is not) or how memory consistency would work in this case. 

 

P.S. The standard clEnqueueRead\WriteBuffer functions have their own return, and can also be configured as non-blocking where an OpenCL event can be used on the host to determine when they finish.
0 Kudos
Altera_Forum
Honored Contributor II
399 Views

I was looking at those but it appeared to me the event were host side only (i.e. they only reported when I finished reading/writing as requested from the host) whereas I would like to know when something has happened on the FPGA; ideally either in the form of data being delivered over the PCI or a flag being set via some other method that alerts me to start a read operation. 

 

If I've misread, I'd be glad to be corrected/pointed at the appropriate documentation.
0 Kudos
Altera_Forum
Honored Contributor II
399 Views

Take a look at the "Stream Data" section of this document (http://sa09.idav.ucdavis.edu/docs/sa09-opencl-dg-events-stream.pdf). Even though this is not true streaming, it will allow you to overlap computation and communication to emulate a similar behavior. I am not sure if you can achieve true streaming without the host channels.

0 Kudos
Reply