Hi all,I have a custom board with a non-SoC Arria10. It is possible to use PCIe as a host interface for non-SoC FPGAs, but this board has all transceiver IO connected to QSFP cages. It also has 1GbE and GPIO pin headers. What are my options to get OpenCL kernels running on this board? Thanks, Dan
Well, you can probably use JTAG or one of the network ports for host interface but you will have to create the OpenCL interface on the FPGA and the driver on the host yourself, and modify the OpenCL runtime to match the new interface. I am pretty sure Altera's SDK and runtime do not support anything other than PCI-E and SoC boards. I highly doubt doing this would be worth the effort, though.If you just want some HLS tool to reduce your design time, you'd probably be better off using one of the existing third-party tools that just generate an HDL module from your c/c++ code without any interface, and then add the necessary interfaces yourself.