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How about a verilog case statement that covers a range?
e.g. : case(xcount) begin 1-100 : junk<=1; 101 : junk<=2; 102-200 : junk<=3; endcaseLink Copied
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SystemVerilog has it using the inside operator
case (xcount) inside
: junk<=1;
101 : junk<=2;
: junk<=3;
endcase
Another nice thing about the case inside statement is that it uses asymmetric wildcard matching. case (xcode) inside
3'b00? : junk<=1;
3'b0?0 : junk<=2;
3'b?00 : junk<=3;
default: junk <='x;
endcase
That means don't cares only match on the case item, not the selecting expression. So if xcode == 3'bx01, the default branch would be taken, not the first branch.
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--- Quote Start --- SystemVerilog has it using the inside operator
case (xcount) inside
: junk<=1;
101 : junk<=2;
: junk<=3;
endcase
Another nice thing about the case inside statement is that it uses asymmetric wildcard matching. case (xcode) inside
3'b00? : junk<=1;
3'b0?0 : junk<=2;
3'b?00 : junk<=3;
default: junk <='x;
endcase
That means don't cares only match on the case item, not the selecting expression. So if xcode == 3'bx01, the default branch would be taken, not the first branch. --- Quote End --- Thanks very much. But I think this "inside" only for SystemVerilog, right?
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Yes. Hopefully if more people ask for it, it will become more widely supported.
To code this in Verilog, you could create an in-between function or macrofunction reg inbetween(input low, value, high);
begin
inbetween = value >= low && value <= high;
end
endfunction
case (1);
inbetween(1,xcount,100): junk<=1;
inbetween(101,xcount,101): junk<=2;
inbetween(102,xcount,200): junk<=3;
endcase
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--- Quote Start --- Yes. Hopefully if more people ask for it, it will become more widely supported. To code this in Verilog, you could create an in-between function or macro
function reg inbetween(input low, value, high);
begin
inbetween = value >= low && value <= high;
end
endfunction
case (1);
inbetween(1,xcount,100): junk<=1;
inbetween(101,xcount,101): junk<=2;
inbetween(102,xcount,200): junk<=3;
endcase
--- Quote End --- Thanks dave. Yes, I think this is very good idea. And this should be able to be synthesized, right?
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--- Quote Start --- SystemVerilog has it using the inside operator
case (xcount) inside
: junk<=1;
101 : junk<=2;
: junk<=3;
endcase
Another nice thing about the case inside statement is that it uses asymmetric wildcard matching. case (xcode) inside
3'b00? : junk<=1;
3'b0?0 : junk<=2;
3'b?00 : junk<=3;
default: junk <='x;
endcase
That means don't cares only match on the case item, not the selecting expression. So if xcode == 3'bx01, the default branch would be taken, not the first branch. --- Quote End --- I added this syntax to an existing SystemVerilog design, but Quartus choked on the "inside" keyword when I tried to build. It's a little ironic, because the Quartus text editor recognizes it as a key word (it shows up in blue). Am I correct in saying that Quartus does not support "case inside"? I do not see it mentioned in the Quartus SV Support documentation.
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It is very easy to recognize a list of keywords to prevent people from using them as identifiers. Supporting the functionality behind them is another story.

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