Have you able to simulate your design? Is there any issue when simulate? The reason is I see compile is successful there I wonder if " # can't read "Startup(-L)": no such element in array" can be ignored.
I'm not able to simulate my design
this message: " # can't read "Startup(-L)": no such element in array" shows after I press the button "start simulation"
Go to the "Library". Find the your verilog file. It should be under work folder. Right click and then click Simulate. This should initialize simulation.
Could you provide the design files and steps taken for me to replicate it? Can attached it here in .qar or email/private message for privacy.