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Hi Llauce,
Have you able to simulate your design? Is there any issue when simulate? The reason is I see compile is successful there I wonder if " # can't read "Startup(-L)": no such element in array" can be ignored.
Thanks,
Regards
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I'm not able to simulate my design
this message: " # can't read "Startup(-L)": no such element in array" shows after I press the button "start simulation"
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anybody can resolve my problem????
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Go to the "Library". Find the your verilog file. It should be under work folder. Right click and then click Simulate. This should initialize simulation.
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Hi Llauce,
Could you provide the design files and steps taken for me to replicate it? Can attached it here in .qar or email/private message for privacy.
Thanks,
Regards
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Hi Sebastian,
Any update from your side regarding this?
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For example in tb
Module tb
Ram (); //wrong way
Ram dut(); // correct way
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