I have a little bit of a problem with some derived clock settings. I'm working on a project where we are using register mode data transfers to the PMA via PCS Direct. The PMA and the data feeding logic therefore must be clocked by the tx_clkout of the Altera transceiver IP. However, for another reason, I must have a slower running clock (100 MHz) edge aligned to the faster 200 MHz clock. I know that we can use an IOPLL hooked up to the same reference clock source to generate the two clock rates I need. However, I'm struggling to coax Quartus to make it edge aligned with the tx_clkout of the PMA. The edge alignment is necessary because we want to avoid a FIFO. Has anyone done this before? And are there any special Quartus settings, SDC commands or special things we need to do to do what we want?
As I understand it, you would like to derive two different clock frequencies from the 200 MHz tx_clkout from the XCVR IP which I believe is the Native PHY. Yes, your understanding is correct, you would need an IOPLL to help derive the two clocks.
Regarding the edge aligned, would you mind to further elaborate on the observation when you use IOPLL to derive the clocks? Since they are derived from the same tx_clkout, there is no ppm concern. Is it that you are observing there are some phase shift between the two output clocks?