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How constraint the output delay from the different clock edge to the same pad?

NuvKFC
New Contributor I
435 Views

I get a ASIC design. And the path structure as follows.

 

Clock_a -----> IP1 use positive edge of Clock_a  ------------> Pad_a: always capture the data on the

                   |                                                                            |                                  positive edge of Clock_a.

                   ---> IP2 use negative edge of Clock_a -----

 

I want to set the output delay from the IP1 to "Clock_a period * 0.5".

And  I also want to set the output delay from the IP2 to "Clock_a period * 0.25" at the same time.

 

How to constraint the output delay on the Pad_a from the different path?

 

Originally, I want to use "-through" command for "set_out_delay" command.

But "set_out_delay" command don't support it.

 

Could someone can help me about this?

Thank you very much.

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7 Replies
NuvKFC
New Contributor I
402 Views

Could someone please give me some help? Thank you very much.

sstrell
Honored Contributor III
396 Views

As discussed in your other post, the clocks are first set up using create_generated_clock constraints.  If you are saying that these generated clocks are output clocks that are used by external devices, then you need additional generated clock constraints to put these clocks at output ports of the device.  Then you create your set_output_delay constraints with the -clock option pointing to these generated clocks.  You also need the correct calculated values for the -max and -min output delay and false path constraints for the clock paths so they are not analyzed as data.  Essentially, you're created a source synchronous output.  See the online training for the details of what you probably need and adjust accordingly:

https://learning.intel.com/developer/learn/course/external/view/elearning/168/constraining-source-sy...

NuvKFC
New Contributor I
279 Views

Hi sstrell

       Thank you, sstrell, very much.

SyafieqS
Moderator
336 Views

Hi KFc,


Are you able to constraint the output delay?



NuvKFC
New Contributor I
280 Views

Hi SyafieqS_Intel

      My method is as follows constraints. I create two virtual clock for the out pin. Then set different output delay for those virtual clock on the output pin. And add false constraint to disable non-exist path.

 

create V1 -period 20 -waveform [0 10]

create V2 -period 10 -waveform [0 5]

 

set_output_delay -max 10 -clock V1 [get_ports Pad_a]

set_output_delay -min 0.0 -clock V1 [get_ports Pad_a]

 

set_output_delay -max 5.0 -clock V2 [get_ports Pad_a]

set_output_delay -min 0.0 -clock V2 [get_ports Pad_a]

 

set_false_path -from [get_clocks Clock_a] -through IP1 to [get_clocks V2]

set_false_path -from [get_clocks Clock_a] -through IP2 to [get_clocks V1]

sstrell
Honored Contributor III
259 Views

I presume you have "create_clock" not just "create" in your design for those virtual clocks.

NuvKFC
New Contributor I
161 Views

Hi sstrell

    Oh. Yes. Sorry that there loss some key words. Thank you very much.

 

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