How do i copy macro

[Fenchia_studentM0907]

Hi I am a student 。

I'm learning Quartus but I have some problems。

I created an A module and used two A modules in the TOP module。
Sorry, so I want to know how to make the same placement and routing of these two modules。

thanks。

My English is not good, so I attach the picture which I drew。

[Nurina]

Hi,

I'm assuming all your modules are in block design files (.bdf) format. If you just add the module A symbol in your top level file then the place and route should not change.

Regards,

Nurina

[Fenchia_studentM0907]

Thanks for your reply。

I design one spi module by using verilog ， in my project  I need to use two SPI Modules.

I hope the place & route of these two are the same because I hope they have the same timing, but according to my understanding, the bdf file is  designed with logic gates, so I think this method maybe not fit my usage situation.

[Nurina]

Hi,

I must apologise, my first reply has a mistake. It's almost impossible to have the same exact place & route for the same two modules in a top level module.

By same timing I'm assuming you're talking about timing closure. You can refer here on what you can do to achieve that:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an584.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an903.pdf

https://www.youtube.com/watch?v=HMAqjjCuDEI

Regards,

Nurina

[Fenchia_studentM0907]

Thank you very much for taking the time to answer my question.

Sorry, I saw qxp file while reading the information a few days ago. I would like to ask if qxp file can achieve my goal.

[Nurina]

Hi,

No, it wouldn't. I suggest using Timing Analyzer, here you will be using .sdc file to set timing constraints. Since your concern is related to place and route, use post-fit netlist when you create timing netlist.

This video lecture explains how you can do that: https://www.youtube.com/watch?v=79mtPfAm1TA&list=RDCMUC0wEPiFb0J6AZZ3oPXRoRpw&index=3

The following videos are part of the same video lecture series which can be useful for you:

https://www.youtube.com/watch?v=6LYvXTaMto0&list=RDCMUC0wEPiFb0J6AZZ3oPXRoRpw&index=11

https://www.youtube.com/watch?v=ggWxledaBFg&list=RDCMUC0wEPiFb0J6AZZ3oPXRoRpw&index=5

I included the first video lecture on my previous reply.

You might find this timing analyzer tutorial to be useful: https://www.intel.com/content/www/us/en/programmable/documentation/caf1499898833805.html

Regards,

Nurina

[Fenchia_studentM0907]

Thank you very much for taking the time to answer me.
I will study the information you gave me, thank you.

[Nurina]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.