Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How does Quartus Prime deal with arrays?

DKirv
Beginner
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I am using VHDL to code a Deo nano SoC. This system has FPGA, CPU and ram. I am focused on the FPGA. I currently am reading data from an outside source and I load the data in a 300 element array. I then changed the array size to 3000 elements and recompiled. I copied the compilation report for both cases and I did not notice a difference in the resources. Where is the FPGA storing the array data and how much room do I have? I am self taught and it was my understanding that data was stored in a form of an IF THEN or similar statement.

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sstrell
Honored Contributor III
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It would help if you posted the code. Device resources get optimized away (or never synthesized at all) if it is determined they are not needed during compilation.

 

#iwork4intel

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DKirv
Beginner
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Here is an example of my code for a larger array.

Where are the elements in the array stored?

 

 

type t_Memory is array (0 to 1023) of std_logic_vector(31 downto 0);

         signal my_array : t_Memory;

signal my_index : integer range 0 to 1023 := 0;

signal my_input   : std_logic_vector(31 downto 0) ;

if flag = 3 then

my_index <= my_index + 1;

my_array(my_index) <= my_input;

end if;

 

if my_index = 1022 then

flag <= 4;

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DKirv
Beginner
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Yesterday, I was writing code and as I changed the parameters of an array, the RAM summary would change accordingly. Now the RAM appears to be utilized by the ALUs. Now I am out of ALU space. Is there a way to explicitly get QP to read/write array elements from RAM?

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DKirv
Beginner
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I found my problem. I had a runaway index.

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