How is memory synthesized by quartus ii ?

[Altera_Forum]

I am using a cyclone ii device (ALTERA DE1 Board by TERASIC) for implementing an application.  

 My application requires approximately 100KB of RAM. I referred to the device datasheet and it says that there is upto 1.1 Mbits of RAM available onchip.   My question is how can I use this onchip ram?  Is it that if I write reg [63:0] mem[4095:0], the synthesis tool will automatically allocate a memory block for me or I will have to do it explicitly?

[Altera_Forum]

Hi, 

 Please have a look at this document: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram_rom.pdf. The fitter will select a suitable position for your design. In addition, you can use i.e. the Assignment Editor to assign a specific location.

[Altera_Forum]

Also see documentation on inferring memory, if you prefer to do it that way. e.g. 

http://quartushelp.altera.com/14.1/mergedprojects/hdl/vlog/vlog_pro_ram_inferred.htm

[Altera_Forum]

From the examples which you have shown, it seems that the tool will synthesize the code by using RAM blocks if I write something like: 

 module ram_single(q, a, d, we, clk); output[7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @(posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; endendmodule And If I write something like  reg [63:0] mem[4095:0];  The tool will be converting this into logic elements. Is this correct??

[Altera_Forum]

--- Quote Start ---  From the examples which you have shown, it seems that the tool will synthesize the code by using RAM blocks if I write something like:  module ram_single(q, a, d, we, clk); output[7:0] q; input [7:0] d; input [6:0] a; input we, clk; reg [7:0] mem [127:0]; always @(posedge clk) begin if (we) mem[a] <= d; q <= mem[a]; endendmodule And If I write something like  reg [63:0] mem[4095:0];  The tool will be converting this into logic elements. Is this correct??  --- Quote End ---    Its not really to do with the size of the array, more to do with how you access it. As long as the code is synchronous and follows the ram tamplates: https://www.altera.co.jp/ja_jp/pdfs/literature/hb/qts/qts_qii51007.pdf  It should infer one large ram (which underneath is made up of lots of smaller rams).

[Altera_Forum]

--- Quote Start ---  The tool will be converting this into logic elements. Is this correct??  --- Quote End ---    In page 11 in the paper I referred earlier (my apologies for referring to an older paper). There are different ways a memory is implemented this can be using dedicated RAM blocks, logic cells etc. By default the fitter selects what it thinks is the best way to fit your design. You can use for example the Assignment Editor to specify if it should use a specific location.