Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to connect 32bit master to 8GB ddr memory using Qsys interconnect.

Artak
Novice
156 Views

 

I'm using a board with Agilex FPGA and 8 GB DDR4 memory.

 

I'm trying to connect a 32bit AXI master (a soft cpu core) to DDR controller in Platform Designer. The Platform Designer interconnect automatically adds AXI-Avalon interface conversion. But I have trouble wiht DDR address range since it requires more than 32 bits to be fully addressed.

Since the master address space is only 32 bit it can't address above 4GB. Is there any way to edit the address map in order to make only the first 2GB of DDR accessible to the master?.

In the address map editor I can modify only the base address of slaves, including DDR memory controller. I could not find any way to set the top address or the address range, the top address is being automatically derived from DDR controller as 8G and is not editable. So I get a connectivity error.
Error: core.Rocket_core_0.mem_axi4_master: dram0_0.ctrl_amm_0 (0x0..0x3ffffffff) is outside the master's address range (0x0..0xffffffff)

How to modify the address range in order to limit DDR access within 0x00000000 -0x80000000?

In Vivado the address map editor allows to define not only the base address but also the address range of each slave item. How the same result can be achieved in Platform Designer?

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1 Solution
Shawn_S_Intel
Employee
98 Views

I recommend the Address Span Extender component. It allows you to set a window into a larger memory space.  The example given in the documentation is your use case:

 

For example, an HPS subsystem in an SoC device can address only 1 GB of an address span within the FPGA, using the HPS-to-FPGA bridge. The Address Span Extender enables the SoC device to address all the address space in the FPGA using multiple 1 GB windows.

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4 Replies
AdzimZM_Intel
Employee
128 Views

Hi Artak,


Thank you for submitting your question in Intel Community.

I am Adzim from Penang Application Engineer will assist you in this thread.


The address map can be changed only for Base address. The End address is already determined with the address range.


"How to modify the address range in order to limit DDR access within 0x00000000 -0x80000000?"

The address range is determined by the Quartus based on the IP setting.

For EMIF IP, the DQ width is main factor to effect the address range.

If you can reduce the DQ width, then the address range will also decrease.


Regards,

Adzim


Shawn_S_Intel
Employee
99 Views

I recommend the Address Span Extender component. It allows you to set a window into a larger memory space.  The example given in the documentation is your use case:

 

For example, an HPS subsystem in an SoC device can address only 1 GB of an address span within the FPGA, using the HPS-to-FPGA bridge. The Address Span Extender enables the SoC device to address all the address space in the FPGA using multiple 1 GB windows.

Artak
Novice
85 Views

Thanks Shawn!

AdzimZM_Intel
Employee
21 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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