How to constraint a clock output

[Benjamin182]

Hi, 

we're evaluating an FPGA design with an AD7961. Analog Devices has an evaluation board where they generated a 100-MHz gated clock from an FPGA. This 100-MHz FPGA gated clock is re-transmitted by the AD7961 and named DCO.

Obviously, I can set up timing constraints between DCO and DO. However, since DCO is derived from my FPGA, how should I proceed?

Regards

[SyafieqS]

Benjamin,

You may need to refer to link below on how to constraint clock.

https://www.youtube.com/watch?v=uYd42q74TLc

[sstrell]

That video doesn't show how to constrain clock outputs from the device.

To constrain an output clock, you have to think of it as source synchronous output clock.

Constraints you need (assuming you've constrained input clocks and are generating the clock output from a PLL):

1) derive_pll_clocks (to create the generated clocks on the outputs of the PLL)

2) create_generated_clock (source is the PLL output pin from get_pins; target is the output port of the device from get_ports; relationship between the two can be -multiply_by 1)

3) create_false_path -to <output port> (so the clock path is not evaluated as a data path)

This training goes into all possibilities for source synchronous inputs and outputs, but what you need is in there:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html

[SyafieqS]

Hi Benjamin,

May I know if there is any updates? Did you able to constrain output clock?