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How to constraint max skew between two net or balance the delay between two net?

NuvKFC
New Contributor I
596 Views

I have two end point (two path) that need to balance the delay.

The design  is as follows.

 

Path1:

    PAD1-->clock of module A: clock_a

 

Path2:

    PAD2-->data of module A: data_a

 

How to constraint the max skew between path1 and path2 or balance the delay between path1 and path2.

 

I had tried following constraint. But it can't work. Thank you very much.

 

Constraint:

set_max_skew 1.0 -from [get_ports {PAD1 PAD2}] \

                                   -to     [get_nets {A|clock_a A|data_a}]]

0 Kudos
1 Solution
Nurina
Employee
333 Views

Hello,


You may refer to this video on how to constraint your design: https://www.youtube.com/watch?v=ggWxledaBFg


Regards,

Nurina


View solution in original post

20 Replies
Nurina
Employee
565 Views

Hi,


Any reason why you put both paths in one constraint?

Did you try two separate constraint like so:

set_max_skew 1.0 -from [get_ports {PAD1}] \

                  -to   [get_nets {A|clock_a}]]

set_max_skew 1.0 -from [get_ports {PAD2}] \

                  -to   [get_nets {A|data_a}]]


Regards,

Nurina


NuvKFC
New Contributor I
549 Views

Hi Nurina

    Thank you, Nurina, very much.

 

The path1 is from PAD1 to clock_a of module A.

The path2 is from PAD2 to data_a of module A. The data_a is one bit data.

 

I hadn't tried to separate constraint. I will try it. And how to report the skew between those two paths?

 

I'm confused that separating the constraint can balance those two paths?

 

Those two paths aren't in the same group like data bus, data[7:0]. 

I'm confusing how to balance the delay of those two paths.

 

Thank you very much

Nurina
Employee
534 Views

Hi,


I don't quite understand the design, could you provide a block diagram?


Regards,

Nurina


NuvKFC
New Contributor I
513 Views

Hi Nurina

    Thank you, Nurina, very much.

 

The design is as follow picture.

PAD1 is used as a clock of module A.

PAD2 is used as a data of module A. And PAD have a multi function. It uses PAD2 as a clock of module B.

 

Some flipflop in the module A use data_a as a clock.

So, I create a clock on node data_a.

I don't want to create a clock for data_a on PAD2 because it will cause many false paths.

Due to that, I constraint data_a on the node data_a of module A.

 

Clock domain data_a and Clock domain clock_a have data crossing.

So, the clock from the data_a and the clock from clock_a is in the same clock group.

(Designer tell me that clock domain data_a and clock domain clock_a should be in the same clock group.)

The detail of constraint of the design is as follow.

 

Design:

NuvKFC_2-1653019430883.png

 

 

Constraint example:

create_clock clock_a [get_port Module_A|clock_a]

create_clock data_a [get_port Module_A|data_a]

 

create_clock clock_b [get_port Module_B|clock_a]

 

create_clock_groups -asynchronous -group [clock_b ]

                                                                    -group [clock_a data_a]

 

 

After Fitter, the net from PAD1 to clock_a and net from PAD2 to data_a become as follow picture.

NuvKFC_1-1653018888921.png


The delay of the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path2)  is unconstrainted.

I add the constraint as follow for these two path.

 

Constraint:

set_net_delay -max 5.0 -from PAD1 to clock_a

set_net_delay -min 0.0 -from PAD1 to clock_a

set_net_delay -max 5.0 -from PAD1 to data_a

set_net_delay -min 0.0 -from PAD1 to data_a

 

And I want to balance the delay between the path from PAD1 to clock_a (Path1) and  the path from PAD2 to data_a (Path1) for the min clock skew between clock domain clock_a and clock domain data_a.

 

But I'm confused how to minimize the clock skew.

The one way I think  is to balance the skew of these two paths.

Then I'm confused how to balance the skew of these two paths.

Nurina
Employee
498 Views

Hello,


Thank you for the clear explanation.


You may find this training video useful: https://www.youtube.com/watch?v=RTcZOl2e8PI


You will have to add a synchronizer chain after path 1 as mentioned in the training video.

Could it be that the set_net_delay constraint is ignored because of a typo? It should be like so, it needs to be "-to" not "to":

set_net_delay -max 5.0 -from PAD1 -to clock_a


For set_max_skew you can try this rather than derive a value as mentioned in the video:

-get_skew_value_from_clock_period


Regards,

Nurina


NuvKFC
New Contributor I
489 Views

Hi Nurina

    Thank you, Nurina, very much.

 

Yes, to is a typo.

 

And how to constraint the path from PAD1 to clock_a (Path1) and  the path from PAD2 to data_a (Path2)?

Path1 and Path2 aren't a grouped paths, like R2 to R3 in the video.

 

I had tried following constraint. But "report_max_skew" command don't report any path.

 

Constraint:

set_max_skew 1.0 -from [get_ports {PAD1 PAD2}] \

                                   -to     [get_nets {A|clock_a A|data_a}]]

 

 

Nurina
Employee
458 Views

Hi,


I think you're suppose to add set_max_skew to the registers R1 & R2 like in this picture:


So then the command should be like so:

set_max_skew -from R1 -to R2 1.0


Regards,

Nurina


NuvKFC
New Contributor I
451 Views

Hi Nurina

    Thank you, Nurina, very much.

 

I can't see the picture. And sorry that I didn't quite catch your point.

 

Where are the R1 and R2 in my design?

 

I can't find any register (R1, R2) on the path from PAD1 to clock_a (Path1) and  the path from PAD2 to data_a (Path2).

 

Thank you very much.

Nurina
Employee
442 Views

Sorry about that. Let me try to re-upload it.

 

NuvKFC
New Contributor I
412 Views

Hi Nurina

    Thank you, Nurina, very much.

 

NuvKFC_0-1654585873123.png

Data_a and Clock_a are in the same clock domain. So, R1 and R2 should meet the setup and hold timing.

If I constraint the skew between R1 and R2 on the previous picture, how to know the path delay (PAD1 to Clock_a, PAD2 to Data_a) meet the requirement? 

 

I only constraint the net delay as follows on the paths which are from PAD1 to Clock_a and from PAD2 to Data_a.

 

Constraint:

set_net_delay -max 5.0 -from PAD1 -to clock_a

set_net_delay -min 0.0 -from PAD1 -to clock_a

set_net_delay -max 5.0 -from PAD2 -to data_a

set_net_delay -min 0.0 -from PAD2 -to data_a

 

AEsqu
Novice
432 Views

You can try using set_min_delay / set_max_delay instead on the ports

NuvKFC
New Contributor I
410 Views

Hi AEsqu

    Thank you, AEsqu, very much.

 

The design and the constraint are as follows.

If I use set_min_delay and set_max_delay on the ports, how to report timing report?

 

Sorry that I have no experience about reporting set_min_delay and set_max_delay constraint on the paths (PAD1 to Clock_a, PAD2 to Data_a).

I only know how to report setup, hold, recovery, removal, and skew in TimeQuest.

NuvKFC_2-1654587075953.png

 

 

Design:

NuvKFC_1-1654586641470.png

 

Constraint:

create_clock Clock_a [get_port Module_A|Clock_a]

create_clock Data_a [get_port Module_A|Data_a]

 

create_clock Clock_b [get_port Module_B|Clock_a]

 

create_clock_groups -asynchronous -group [Clock_b ]

                                                                    -group [Clock_a Data_a]

 

set_net_delay -max 5.0 -from PAD1 -to Clock_a

set_net_delay -min 0.0 -from PAD1 -to Clock_a

set_net_delay -max 5.0 -from PAD2 -to Data_a

set_net_delay -min 0.0 -from PAD2 -to Data_a

AEsqu
Novice
388 Views

Try with report path from the GUI (Quartus 22.1.0)

Example:

report_path -from [get_ports {IO1_SWM10}] -npaths 100 -panel_name {Report Path} -multi_corner

 

NuvKFC
New Contributor I
376 Views

Hi AEsqu

    Thank you, AEsqu, very much.

 

I will try it. Thank you very much.

Before that, I have two questions in follows.

 

(1)Do I need manually report the path every time after compiling done to check that the path timing is correct?

 

(2)If I use set_min_delay and set_max_delay on the ports, how to know that the min delay value and the max delay value make sense?

     For example, as follows constraints, both case(1) and case(2) limit the max skew to 1 ns.

     But which case make sense more?

 

    Constraints:

    case(1):

    set_max_delay  5.0 -from PAD1 -to Clock_a

    set_min_delay  4.0 -from PAD1 -to Clock_a

 

    set_max_delay  5.0 -from PAD2 -to Data_a

    set_min_delay  4.0 -from PAD2 -to Data_a

 

    case(2):

    set_max_delay 100.0 -from PAD1 -to Clock_a

    set_min_delay  99.0    -from PAD1 -to Clock_a

 

    set_max_delay 100.0 -from PAD2 -to Data_a

    set_min_delay  99.0    -from PAD2 -to Data_a

AEsqu
Novice
369 Views

For my use case where I was playing with set_min_delay and set_max_delay

is where I was bringing a clock out from the FPGA towards a pin, that was used by another Chip.

I made sure that the clock rising edge occured after the DATA outputs were already stable.

So I added a bit more delay on the clk output compare to the data output and that was working fine (the data outputs were driven by the FPGA on the same internal clk). 

Example:

   set RF_SPI_CLK_MIN_DELAY 7.0
   set RF_SPI_CLK_MAX_DELAY 11.0
   set RF_SPI_EXTRA_MIN_DELAY   [expr {$RF_SPI_CLK_MIN_DELAY+5.0}]
   set RF_SPI_EXTRA_MAX_DELAY   [expr {$RF_SPI_CLK_MAX_DELAY+5.0}]
   
   set_min_delay -to $rf_spi_clk_port $RF_SPI_CLK_MIN_DELAY
   set_max_delay -to $rf_spi_clk_port $RF_SPI_CLK_MAX_DELAY
   
   set_min_delay -to $rf_spi_mosi_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -to $rf_spi_mosi_port $RF_SPI_EXTRA_MAX_DELAY
   
   set_min_delay -to $rf_spi_cs_n_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -to $rf_spi_cs_n_port $RF_SPI_EXTRA_MAX_DELAY
   
   set_min_delay -from $rf_spi_miso_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -from $rf_spi_miso_port $RF_SPI_EXTRA_MAX_DELAY
NuvKFC
New Contributor I
348 Views

Hi AEsqu

    Thank you, AEsqu, very much.

 

Recently,  I get an information that both set_min_delay and set_max_delay only work on the path which has setup/hold relationship.

 

Could you please tell me how you to constraint your clock or constraint the setup/hold relationship.

Thank you very much.

Nurina
Employee
334 Views

Hello,


You may refer to this video on how to constraint your design: https://www.youtube.com/watch?v=ggWxledaBFg


Regards,

Nurina


NuvKFC
New Contributor I
320 Views

Hi Nurina

    Thank you, Nurina, very much. I will see it. Thank you very much.

Nurina
Employee
299 Views

Hello,


No worries! I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Nurina


P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.


NuvKFC
New Contributor I
284 Views

Hi Nurina

    Thank you, Nurina, very much. OK. Thank you very much.

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