How to deal with glitch free clock switch when use auto gated clock conversion?

[NuvKFC]

I get an ASIC design which contains many glitch free clock switch as follows picture. When I use auto gated clock conversion option, tool said that it's an unsupported cascaded clock so that tool can't convert it.

Could someone have the experience to share with me? Thank you very much.

[NuvKFC]

Whether someone has the experience to share please? Thank you very much.

[SyafieqS]

Hi KFc, 

What device are you using for ASIC prototyping? 

Auto Gated Clock Conversion logic option only available Arria series, Cyclone II, Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix V) families. You need to double check this.

[NuvKFC]

Hi SyafieqS_Intel

        Thank you, SyafieqS_Intel, very much. I'm using  Stratix IV. But tool said that it's an unsupported cascaded clock so that tool can't convert it.

[SyafieqS · Accepted solution]

Hi KFC,

Can you refer to below document. Make sure all the requirement are met in order to convert gated clock.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-compiler.pdf#page=143

[NuvKFC]

Hi SyafieqS_Intel

    Thank you very much.