Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
15674 Discussions

How to deal with glitch free clock switch when use auto gated clock conversion?

NuvKFC
New Contributor I
429 Views

I get an ASIC design which contains many glitch free clock switch as follows picture. When I use auto gated clock conversion option, tool said that it's an unsupported cascaded clock so that tool can't convert it.

NuvKFC_0-1635304699210.png

 

Could someone have the experience to share with me? Thank you very much.

0 Kudos
1 Solution
SyafieqS
Moderator
267 Views

Hi KFC,


Can you refer to below document. Make sure all the requirement are met in order to convert gated clock.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-compiler.pdf#page...


View solution in original post

5 Replies
NuvKFC
New Contributor I
400 Views

Whether someone has the experience to share please? Thank you very much.

SyafieqS
Moderator
340 Views

Hi KFc, 


What device are you using for ASIC prototyping? 

Auto Gated Clock Conversion logic option only available Arria series, Cyclone II, Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix V) families. You need to double check this.


NuvKFC
New Contributor I
295 Views

Hi SyafieqS_Intel

        Thank you, SyafieqS_Intel, very much. I'm using  Stratix IV. But tool said that it's an unsupported cascaded clock so that tool can't convert it.

SyafieqS
Moderator
268 Views

Hi KFC,


Can you refer to below document. Make sure all the requirement are met in order to convert gated clock.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-compiler.pdf#page...


NuvKFC
New Contributor I
188 Views

Hi SyafieqS_Intel

    Thank you very much.

Reply