I would like to disable the ECC check which occurs at the beginning of the Cyclone V boot process in order to save boot time. However, the only way I currently know how to do this is to edit the "CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN" and "CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN" defines to "0" within the file "board/altera/socfpga_cyclone5/sdram/sdram_config.h" prior to building the preloader. This is annoying because the values get reset if I regenerate the BSP settings.
Is there a way to disable this check in either Quartus or the BSP Editor without manually modifying the preloader source?
If you want to disable ECC, you can disable it in Qsys/Platform Designer, then the preloader will also disable it.
If you want to enable ECC, BUT disable the ECC checking, I am unsure if this is possible using the BSP Editor to generate, you may need to generate your own custom preloader.
You may read the preloader customization information here, it's helpful: