How to disable most synthesis-optimizations options?

[JRoit]

I'm trying to implement some Butterfly-PUF cells on a Altera FPGA with Quartus II. For some reason my Butterfly-PUF-cells are "optimized" to a simple inverter.

Does anyone know how to disable most synthesis-optimizations options?

You can find my Quartus II Projekt below.

I'm really looking forward to our answers.

Regards

Johannes

[Abe]

Looking at the schematic in your design, I see the following :

For the Butterfly_Zellen Schematic

1. Clock pins are tied to GND
2. PRE and CLR are tied together to VCC for both DFF blocks
3. PRE and CLR are tied together and given as Input to both DFFs.

What are you trying to achieve by doing this? If the CLK pins are tied to GND or VCC the DFF will not work and will be always OFF. Plus, since the PRE and CLR are tied together and have opposite functions, when you set this to VCC or GND, one DFF will be cleared while the other one will be Preset.

Please check your connections. If the connections are incorrect, the tool will analyze the circuit and if it determines that any of the inputs/outputs are stuck at '0' or '1' it will remove / optimize away the logic.

[JRoit]

Hello Abe,

thank you for your answer and for looking at my project.

I want to implement butterfly PUF Cells as introduced in https://www.researchgate.net/publication/4349783_Extended_abstract_the_butterfly_PUF_protecting_IP_on_every_FPGA

Yes, you're right. I have made a mistake.

1. Clock should be always high

2. PRE of FF 1 and CLR of FF 2 should be always low

But after this changes Quartus removes my Butterfly-Cells and connects the SZx_Out Pins to GND and i still don't know why... Quartus tells me "Warning (13024): Output pins are stuck at VCC or GND"

I have already implemeted Butterfly-Cells on an Xilinx Spartan3e FPGA with Xilinx ISE with the same vhdl Files and it worked just fine.

You can find a version with correct conected Butterfly-Cells below.

Best regards

Johannes