Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to disable the following things in QuartusII

Altera_Forum
Honored Contributor II
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Hi, 

 

I am having trouble finding where to change the settings in QuartusII to achieve the following 2 things : 

1. To disable the transformation of chains of registers into a shift-register primitive. 

2. To disable placement of I/O registers into the device pin registers. Right now the placement is happening such that there are long combinational paths which are not good for the design. 

 

I am held up because of this :( . Your replies will be of great help to me.  

 

Thanks.
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Altera_Forum
Honored Contributor II
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1. Assignments -> Settings -> Analysis & Synthesis -> More Settings -> Auto Shift Register Replacement = Off 

(You can also locate hierarchies to the Assignment Editor and disable/enable at a hierarchical level.) 

2. With no changes to the project, there is nothing that forces I/O register usage, unless using a primitive like altddio_in/out. Otherwise, the fitter has the option to use the I/O register in order to improve timing. So if you have timing constraints, it tends to pull the registers into the I/O. If you have loose I/O constraints but tight internal constraints on these long comb paths(I assume from I/O to I/O), then it should be able to pull them into the fabric. I've seen this work before. Is your internal logic failing timing?  

In the absense of any timing constraints, I think it will use the I/O registers just to save space, since you're not really telling it what to do. Also, if the internal constraints aren't tight, it tends to use them. 

If you really don't want them, you can go into the Assignment Editor and assign to the specific I/O port, Fast Input Register = Off. There's a Fast Output Register assignment too.
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