Hi,How to ensure a value "CAFE" on the register Reg_In with the RTL code:Reg_In <= X"CAFE" when A = '1' else In_1 when K = '1 else In_2 when L = '1' else In_3 when M = '1' else Bus; A is driven by register output. K,L and M are results of several logic functions driven by registers. All registers are in the same clock domain. Bus is an asynchronous in/output and also used in other parts of the design. Thus, when A is set the In must be forced to "CAFE", despite of changes on the Bus signal. The device I'm using is a Cyclone III and the SW version is 13.1 The implementation: The low Reg_In byte is always set to "FE", the high byte is not set to "CA" sometimes. How to ensure the priority of the multiplexer in VHDL? Or other options? Thx. BaSt
During synthesis and fitting the whole design is taken into account.This results in the behavior: "The low Reg_In byte is always set to "FE", the high byte is not set to "CA" sometimes." The question is: how can this be avoided? In VHDL or with other options in Quartus?
Quartus will only synthesise what you write.The snippet you posted says that Reg_in will be x"CAFE" when A = 1. If you are having problems, then I suggest there is a problem in the design somewhere. Where are you seeing the problems? simulation, or on the board? Without the whole code, there isnt much more I can say.
The error occurs on the board. Simulation is OK.In SignalTap I saw the change of the high byte of Bus reflected in some of the bits of the Reg_in data input. In the Technology Map view, the implementation of the low byte part of the multiplexer is according the VHDL. The high byte is mapped differently. The input for A is half way the mapped multiplexer structure and not in the last stage of the multiplexer as described in the RTL code. Why is this done this way? How to overcome, force the right RTL implementation?