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How to fix lut4 input ports?

hzs268
Beginner
275 Views

I need to implement a arbiter puf in cycloneive fpga, with the requirement of extreamly net delay parameter about less than 100ps. 

 

I know that chip planner can change the lut input port in gui display, but I want to fix the lut4 input port in rtl code or any tcl script because of there are many mux implemented by lut4 in my design, using gui is very unefficient.

 

I have tried to use WYSIWYG LCELLS in rtl code like this,but after fitting, the lut4 input ports changed:

2022_05_18_12_52_30.png

-----

    cycloneive_lcell_comb lut4 (
        .dataa                             (i_data[0]                       ),
        .datab                             (i_data[1]                       ),
        .datac                             (i_sel                           ),
        // .datad                             (1'b0                            ),
        // .cin                               (1'b0                            ),
        // .cout                              (                                ),
        .combout                           (o_data                          )
    );
    defparam    lut4.lut_mask = 16'hCACA,
                lut4.dont_touch = "on",
                lut4.lpm_type = "cycloneive_lcell_comb",
                lut4.sum_lutc_input = "datac";
-----
 
And I also tried to export the chip planner change manager with a tcl file, but when I fit the design again and import the tcl, it always ocure error in Quartus 18.1.
2022_05_18_12_56_11.png2022_05_18_13_00_21.png2022_05_18_13_09_01.png2022_05_18_13_09_11.png
 
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5 Replies
sstrell
Honored Contributor III
259 Views

Can you better explain what you're trying to accomplish here?  What is an "arbiter puf"?  You should be looking at your HDL code and timing constraints, not trying to make low-level post-fit changes.

SyafieqS
Moderator
246 Views

Alternatively, you should be looking at timing constraint e.g set_net_delay. Use the set_net_delay command to query the net delays

and perform minimum or maximum timing analysis across nets of <0.1ns



hzs268
Beginner
237 Views

Thanks a lot SyafieqS!

 

I tried to lock my design LUT location by 'set_location_assignment' for identical net delay between every PUF mux slice.

The 'set_net_delay' constraint works after I delete the constraint of LUT location, let Quartus fit according to the timing constraint.

 

Now the net delay between PUF mux slice is very close and achieve my goal.

 

PUF.png

2022_05_19_17_40_20.png

SyafieqS
Moderator
193 Views

Hi Huang,


Glad you able to resolve it. Let me know if there is any update or any other concern.


SyafieqS
Moderator
170 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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