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How to fully constrain a design with several synchronous clock domains?


My design only has one clock. I use a cyclic shift register containing only a single 1 to generate enable signals used to divide the Frequency. I use a 4 bit shift register to create 4 enables out of a 400 MHz clock. So aside from the fast clock I have four 100 MHz clock domains. I use all five clocks in my design. I there a way to make Timequest automatically recognize this instead of having to create a bunch multicycle path exceptions by hand?



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You may refer to AN 433: Constraining and Analyzing Source-Synchronous Interfaces for constraining the source synchronous interface.


You have to apply:


  • Clock constraints: Describe the required times for data to be valid at the interface
  • Input or output delay constraints; either in System-centric method or FPGA-centric method: Describe the required times for data to be valid at the interface. 
  • Timing exceptions: Control launch and latch edges used in timing analysis. Timing exceptions ensure that valid timing paths in the interface are analyzed, and invalid paths are not analyzed.


Please let me know if you have any questions.