My design only has one clock. I use a cyclic shift register containing only a single 1 to generate enable signals used to divide the Frequency. I use a 4 bit shift register to create 4 enables out of a 400 MHz clock. So aside from the fast clock I have four 100 MHz clock domains. I use all five clocks in my design. I there a way to make Timequest automatically recognize this instead of having to create a bunch multicycle path exceptions by hand?
You may refer to AN 433: Constraining and Analyzing Source-Synchronous Interfaces https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf for constraining the source synchronous interface.
You have to apply:
Please let me know if you have any questions.