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Altera_Forum
Honored Contributor I
1,545 Views

How to generate two non overlapping clock signals from single clock?

In a design I'd like to use both edges of an external clock signal (EXT_CLK). 

No other clock signals are available. Now the question: 

 

Is it possible to generate two signals 

 

CLK1 == EXT_CLK and 

CLK2 == !EXT_CLK 

 

such that both signals are not high at the same time and such that 

the resulting verilog code is not device/architecture specific? 

 

 

Please excuse if this is a dumb question.
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4 Replies
Altera_Forum
Honored Contributor I
227 Views

How about: 

 

assign CLK1 = EXT_CLK & ~CLK2; 

assign CLK2 = !EXT_CLK & ~CLK1; 

 

which is basically how one does this using cross-coupled NAND gates in discrete TTL logic. 

 

That being said, if CLK1 and CLK2 are to be distributed over a wide area (large number of loads) controlling skew to guarantee they will be nonoverlapping at all loads will be problematic. It will require timing constraints for layout, and you may find as the design progresses that some layouts fail to meet timing as the placement/routing changes. 

 

All in all I would say this is NOT a good design approach and I would look to find a solution that relies on logic using a single distributed clock where you use both edges, as appropriate, for local clocking.
Altera_Forum
Honored Contributor I
227 Views

Doing logic with the clock is pretty much a no-no in FPGAs. The skew will just kill it. 

 

Why not just derrive a 2x EXT_CLK using a PLL? You can lock the PLL so that it is in sync with EXT_CLK.
Altera_Forum
Honored Contributor I
227 Views

 

--- Quote Start ---  

Doing logic with the clock is pretty much a no-no in FPGAs. The skew will just kill it. 

Why not just derrive a 2x EXT_CLK using a PLL? You can lock the PLL so that it is in sync with EXT_CLK. 

--- Quote End ---  

 

 

Thanks for the answers! 

 

The FPGA should connect to an old system that is using a two phase non-overlapping clock and this clock is 

too low to be used for the PLL. 

 

Just a last question (for now): 

 

What is better if I want to use both edges of the clock in a design: 

 

1. using always @ (posedge CLK) and always @ (negedge CLK) or 

2. using @ (posedge CLK) and @(posedge CLK_n) 

3. both variants 1+2 are just equivalent? 

 

Thanks!
Altera_Forum
Honored Contributor I
227 Views

if the clock is that slow (<2Mhz) , it might just be easier to use some much faster system clock (like 50Mhz) and sample both the clock and data lines. Wait for a rising edge edge of either clock and just sample the data bus.

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