How to handle multiple files with the same name?

[ldm_as]

Hello,

How to handle multiple RTL files (Verilog) with the same name?

Actually I receive deliveries from different sources, which use the same file names and module names in their designs (but context of the files are different).

So, how to handle this situation? Could the files be compiled to the different libraries since they belong to the different units (but within the same project)? How to do so?

Thanks!

[ShyanYew_T_Intel]

Quartus can't handle multiple RTL files with the same name unfortunately. It requires that the name to be distinct for each library.

Reference: Ensure Distinct VHDL Namespace for Each Library.