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15317 Discussions

How to implement DP RAM written in RTL using M20K?

AGaru1
Beginner
175 Views

Hi all,

can you please help me to synthetize a ram module written in vhdl as M20K? Unfortunately Quartus is synthetizing it using flipflops so it ends up in a big waste of them. Is there any particular attribute to write on the rtl or any constraints to specify on the qsf file? Or also any particular coding style for the rtl in order to make it possible? I want to avoid using the Intel DP RAM from the Altera library because the timings are different and a great modification of the design would be required.

Thank you so much.

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2 Replies
Kenny_Tan
Moderator
142 Views

Yes, what you can do is right click on the vhdl/verilog files, insert template.

 

From there, you can find the method to rewrite the code for your ram and there is also attribute that you can use to infer M20k

AGaru1
Beginner
142 Views

Thank you so much, i didn't know that.

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